tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 47

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

(output)
(input)
CMD
Initialization
and SCK are transmitted by the controller and are received by each XDR DRAM device along the bus. The signals
are terminated to the VTERM supply through termination components at the end farthest from the controller. The
SDI input of the XDR DRAM device furthest from the controller is also terminated to VTERM. The SDO output of
each XDR DRAM device is transmitted to the SDI input of the next XDR DRAM device (in the direction of the
controller). This SDO/SDI daisy-chain topology continues to the controller, where it ends at the SRD input of the
controller. All the serial interface signals are low-true. All the signals use RSL signaling circuits, except for the
SDO output which uses CMOS signaling circuits.
Figure 47. Serial Interface Systems Topology
above. Prior to initialization, the RST is held at zero. The CMD input is not used here, and should also be held at
zero. Note that the inputs are all sampled by the negative edge of the SCK clock input. The SDI input for the XDR
DRAM [0] device is zero, and is unknown for the remaining devices.
zero on edge S
device are set to their reset values after the first edge (S
Figure 48. Initialization Timing for XDR DRAM [ k ] Device
SDO
DRAMs except for XDR DRAM [0]. XDR DRAM [0]’s SDI input will always be sampled zero.
SCK
RST
SDI
RST
Figure 47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD,
Figure 48 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown
On negative SCK edge S
The SDI inputs will be sampled one within a time t
0
1
0
1
0
1
0
1
0
1
Controller
Power On t
CMD
12
SCK
SRD
a time t
COREINIT
RST-10
8
SDO
RST
the RST input is sampled one. It is sampled one on the next four edges, and is sampled
S
0
XDR DRAM
after it was first sampled one. The state of the control registers in the XDR DRAM
S
2
CMD
S
‘0' ‘0' ‘0' ‘0' ‘1' ‘1' ‘1' ‘1' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'
‘x' ‘x' ‘x' ‘x' ‘X' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1'
‘x' ‘x' ‘x' ‘x' ‘X' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘1' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'
4
SCK
S
SDI
6
S
8
t
t
RST-10
RST-SDO,11
TC59YM916BKG24A,32A,32B,40B,32C,40C
S
10
RST-SDO, 11
S
12
t
8
RST,SDI,00 = k *
) in which RST is sampled one.
S
14
SDO
RST
S
‘0'
XDR DRAM
16
‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0' ‘0'
after RST is first sampled one in all the XDR
t
CMD
S
SDI-SDO,00
18
t
CYC,SCK
S
20
SCK
SDI
S
22
S
24
S
26
S
28
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SDO
RST
S
30
t
XDR DRAM
CYC,SCK
S
32
CMD
VTERM
S
34
Rev 0.1
S
SCK
36
SDI
S
38