tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 71

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Serial Interface Receive Timing
a magnified view of the pins only a few clock cycles.
represents a logical one. Timing events are measured to and from the V
measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise time (t
and fall time (t
a set time (t
Figure 61. Serial Interface Receive Waveforms
SMD
SCK
RST
SDI
Figure 61 shows a timing diagram for the serial interface pins of the memory component. This diagram represents
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage
There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has
t
F,SCK
20% = V
50% = V
80% = V
S,RQ
F,SCK
IL, SI
IL, SI
IL, SI
t
L,SCK
) and a hold time (t
+ 0.2 × (V
+ 0.5 × (V
+ 0.8 × (V
and t
IF,SI
t
CYC,SCK
IH,SI
IH,SI
IH,SI
t
R,SCK
) of the signals are measured from the 20% and 80% points of the full-swing levels.
− V
− V
− V
H,RQ
IL,SI
IL,SI
IL,SI
) measured around the falling edge of the SCK clock signal.
)
)
)
t
H,SCK
t
RI,SI
TC59YM916BKG24A,32A,32B,40B,32C,40C
t
S,SI
t
H,SI
t
FI,SI
REF, RSL
level. Because timing intervals are
2004-12-15 71/76
R,SCK
Rev 0.1
and t
Logic 0
V
80%
V
20%
V
Logic 1
Logic 0
V
80%
V
20%
V
Logic 1
RI,SI
IH,SI
REF,RSL
IL,SI
IH,SI
REF,RSL
IL,SI
)