tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 52

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Special Feature Description
Dynamic Width Control
so that read and write data can be accessed through differing widths of DQ pins. Figure 46 shows a diagram of the
logic in the path of the read data (Q) and write data (D) that accomplishes this.
sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is configured for
maximum width operation (using the WIDTH [2:0] field in the CFG register), each set of 16 S signals goes to one of
the 16 DQ pins (via the Q [15:0] [15:0] read bus) and are driven out in the 16 time slots for a read data packet.
used and the rest are not used. The SC [3:0] field of the COL request packets selects which S [15:0] [15:0] signals
are passed to the Q [15:0] [15:0] read bus and driven as read data.
SC [3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH [2:0]. In each
table, there is an entry in the left column for each valid value of SC [3:0]. This field should be treated as an
extension of the C [9:4] column address field. The right hand column shows which sets of S [15:0] [15:0] signals are
mapped to the Q read data bus for a particular value of SC [3:0].
appropriate table in Figure 47, it may be seen that in the SC [3:0] field, the SC [1:0] sub-column address bits are
not used. The remaining SC [3:0] address bit(s) selects one of the 64-bit blocks of S bus signals, causing them to be
driven onto the Q [3:0] [15:0] read data bus, which in turn is driven to the DQ3…DQ0/DQN3…DQN0 data pins.
The Q [15:4] [15:0] signals and DQ15…DQ4/DQN15...DQN4 data pins are not used for a device width of x4.
bus connecting to the sense amps of the memory core), with 16 signals in each set. When the XDR DRAM device is
configured for maximum width operation (using the WIDTH [2:0] field in the CFG register), each set of 16 S signals
is driven from one of the 16 DQ pins (via the D [15:0] [15:0] write bus) from each of the 16 time slots for a write
data packet.
the SC [3:0] field of the COL request packet. There is a separate table for each valid value of WIDTH [2:0]. In each
table, there is an entry in the left column for each valid value of SC [3:0]. This field should be treated as an
extension of the C [9:4] column address field. The right hand column shows which set of S [15:0] [15:0] signals are
mapped from the D read data bus for a particular value of SC [3:0].
appropriate table in Figure 47, it may be seen that in the SC [3:0] field, the SC [0] sub-column address bit is not
used. The remaining SC [3:0] address bit(s) selects one of the 32-bit blocks of S bus signals, causing them to be
driven from the D [1:0] [15:0] write data bus, which in turn is driven from the DQ1…DQ0/DQN1...DQN0 data pins.
The D [15:2] [15:0] signals and DQ15…DQ2/DQN15…DQN2 data pins are not used for a device width of x2.
Figure 49. Multiplexes for Dynamic Width Control
This XDR DRAM device includes a feature called dynamic width control. This permits the device to be configured
The read path is on the right of the figure. There are 16 sets of S signals (the internal data bus connecting to the
When the XDR DRAM device is configured for a width that is less than the maximum, some of the DQ pins are
Figure 50 shows the mapping from the S bus to the Q bus as a function of the WIDTH [2:0] register field and the
For example, assume that the WIDTH [2:0] value is “010”, indicating a device width of x4. Looking at the
The write path is shown on the left side of Figure 46. As before, there are 16 sets of S signals (the internal data
Figure 50 also shows the mapping from the D bus to the S bus as a function of the WIDTH [2:0] register field and
For example, assume that the WIDTH [2:0] value is “001”, indicating a device width of x2. Looking at the
WIDTH [2 : 0]
SC [3 : 0]
M [7 : 0]
4+3
8
Dynamic Width Demux (WR)
16x16
16x16
16x16
Byte Mask (WR)
D [15:0] [15:0]
TC59YM916BKG24A,32A,32B,40B,32C,40C
D1 [15:0] [15:0]
S [15:0] [15:0]
Dynamic Width Mux (RD)
16x16
16x16
Q [15:0] [15:0]
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4+3
Rev 0.1
WIDTH [2 : 0]
SC [3 : 0]