tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 7

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Pin Description
supply voltages. These include VDD and GND for the core and interface logic, VREF for receiving input signals,
and VTERM for driving output signals.
DQN15...DQN0 for carrying read and write data signals, RQ11...RQ0 for carrying request signals, and CFM and
CFMN for carrying timing information used by the DQ, DQN, and RQ signals.
initializing the state of the device, CMD for carrying command signals, SDI and SDO for carrying register read
data, and SCK for carrying the timing information used by the RST, SDI, SDO, and CMD signals.
Table 1 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary
The next group of pins is used for high bandwidth memory accesses. These include DQ15…DQ0 and
The final set of pins comprises the serial interface that is used for control register accesses. These include RST for
a. J6 / J11 / C6 / C11 are optional balls. This table represent a superset across all the generations and densities pf XDR DRAM.
b. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
c. H1 / H16 / D1 / D16 are depopulated balls.
DQN15…DQN0
DQ15…DQ0
RQ11…RQ0
All DQN, CFMN, RQ, RSL and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
V TERM
Signal
CFMN
V REF
RSRV
Total pin count per package
GND
CMD
V DD
CFM
SDO
RST
SCK
SDI
I/O
I/O
I/O
⎯
⎯
⎯
⎯
⎯
O
I
I
I
I
I
I
I
DIFFCLK
DIFFCLK
CMOS
DRSL
DRSL
RSL
RSL
RSL
RSL
RSL
Type
⎯
⎯
⎯
⎯
⎯
b
b
b
b
b
b
b
b
b
b
No. of Pins
100/(108)
26
22
Table 1. Pin Descriptions
6
16
16
12
1
1
1
1
1
1
1
1
2
a,c
a
c
TC59YM916BKG24A,32A,32B,40B,32C,40C
Supply voltage for the core and interface of the device.
Ground reference for the core and interface logic of the device.
Logic threshold reference voltage for RSL signals.
Termination voltage for DRSL signals.
Positive data signals that carry write or read data to and from the device.
Negative data signals that carry write or read data to and from the device.
Request signals that carry control and address information to the device.
Clock from master – Positive interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
Clock from master – Negative interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
Reset input – This pin is used to initialize the device.
Command input – This pin carries command, address, and control register
write data into the device.
Serial clock input – Clock source used for reading from and writing to the
control registers.
Serial data input – This pin carries control register read data through the
device. This pin is also used to initialize the device.
Serial data output – This pin carries control register read data from the
device. This pin also used to initialize the device.
Reserved pins – Follow Rambus XDR system design guidelines for
connecting RSRV pins.
Description
2004-12-15 7/76
Rev 0.1