ak4372 ETC-unknow, ak4372 Datasheet - Page 22

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

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The AK4372 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the
master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling
frequency and MCKI frequency can be selected by FS3-0 bits
output is enabled by MCKO bit. The MCKO output frequency can be controlled by PS1-0 bits. If the sampling frequency
is changed during normal operation of the DAC (PMDAC bit = “1”), the input must be muted by SMUTE bit = “1”, or set
to “0” data.
LRCK and BICK are output from the AK4372 in master
always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the
AK4372 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic
refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit =
“0”).
The external clocks required to operate the AK4372 in slave mode are MCKI, LRCK and
clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter.
All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4372 may draw excessive current and will not operate
properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the
DAC should be placed in power-down mode (PMDAC bit = “0”).
MS0684-E-02
EXT Mode (PMPLL bit = “0”: Default)
AK4372
AK4372
MCKO
MCKI
BICK
LRCK
SDATA
MCKO
MCKI
BICK
LRCK
SDATA
Figure 15. EXT Master Mode
Figure 16. EXT Slave Mode
256fs, 384fs, 512fs,
768fs or 1024fs
256fs, 384fs, 512fs,
768fs or 1024fs
32fs, 64fs
32fs, 64fs
mode(Figure
1fs
1fs
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(Table
11). In EXT mode, PLL4-0 bits are ignored. MCKO
15). The clock input to the MCKI pin should
MCLK
BCLK
LRCK
SDTO
MCLK
BCLK
LRCK
SDTO
DSP or μP
DSP or μP
BICK(Figure
16). The master
[AK4372]
2008/12