ak4372 ETC-unknow, ak4372 Datasheet - Page 40

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

2) DAC → Lineout
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
(2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to
(5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these
(6) DALL and DARR bits should be changed to “1” after the PLL is locked
(7) PMLO bit is changed to “1”.
(8) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(9) Analog output corresponding to the digital input has group delay (GD) of 22fs(=499μs@fs=44.1kHz).
(10) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0684-E-02
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks.
Power Supply
PDN pin
PMVCM, PMPLL,
PMDAC, MCKO bits
MCKI pin
MCKO pin
BICK, LRCK pins
DAC Internal
SDTI pin
DALL,
DARR bits
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
State
Figure 33. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
Don’t care
Don’t care
Unstable
Don’t care
10H(MUTE)
(1) >150ns
PD
(Hi-Z)
(2)>0s
(6) >0s
00H(MUTE)
Unstable
Unstable
Unstable
(3)
Table
(4) ~20ms
(7) >0s
(5)
4. After the PLL is locked, the MCKO pin outputs the master clock.
(8)
(9) GD (10) 1061/fs
Normal Operation
FFH(0dB)
- 40 -
(9) (10)
Unstable
Don’t care
Don’t care
0FH(0dB)
00H(MUTE)
Unstable
Unstable
(8)
PD
(6) >0s
Unstable
(Hi-Z)
(4) ~20ms
(5)
(7) >0s
(8)
Normal Operation
(9)
(10)
FFH(0dB)
[AK4372]
2008/12