ak4372 ETC-unknow, ak4372 Datasheet - Page 33

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ak4372

Manufacturer Part Number
ak4372
Description
Dac With Built-in Pll & Hp-amp
Manufacturer
ETC-unknow
Datasheet
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LINL, RINL and MINL bits control each path switch of LOUT. DARR, LINR, RINR and
MINR bits control each path switch of ROUT. When LM bit = “0”, LOG bit = “0” (R
bits is “0FH”(0dB), the mixing gain is 0dB(typ) for all paths. When the LOG bit = “1”(R
+6dB. When LM bit = “1”, LIN and RIN signals are output from LOUT/ROUT pins as (L+R)/2 respectively.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally.
MS0684-E-02
Stereo Line Output (LOUT, ROUT pins)
MIN pin
MIN pin
RIN pin
RIN pin
LIN pin
LIN pin
DAC Rch
DAC Lch
DARR bit
DALL bit
RINR bit
MINR bit
RINL bit
MINL bit
LINR bit
LINL bit
Figure 26. Summation circuit for stereo line output
Figure 51
R
R
R
R
R
R
R
R
1L
1L
2L
DL
1L
1L
2L
DL
shows the external bias circuit example.
100k(typ)
100k(typ)
+
+
- 33 -
R
R
L
L
+
+
R
R
L
L
1L
= R
DL
2L
= 50k), the DAC path gain is
= R
DL
= 100k) and ATTS3-0
LOUT pin
ROUT pin
[AK4372]
2008/12

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