78m6618-imr/f/p Maxim Integrated Products, Inc., 78m6618-imr/f/p Datasheet - Page 12

• Manufacturer Part Number: 78m6618-imr/f/p
• Description: Octal Power And Energy Measurement Ic
• Manufacturer: Maxim Integrated Products, Inc.

78M6618 Data Sheet
The SPI port supports data transfers at up to 1 Mb/s. The SPI commands are described in Table 1 and
Figure 3 illustrates the SPI Interface read and write timing.
Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU or IORAM
but not SFRs or the 80515-internal register bank. See the 78M6618 Programmer’s Reference Manual for
more information regarding the mapping and use of SPI functions.
1.19 Test Port
One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. See the
78M6618 Programmer’s Reference Manual for more information regarding the use of TMUXOUT.
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11xx xxxx ADDR D0 ... DN
1100 0000 ADDR D0 ... DN
11xx xxxx ADDR D0 ... DN
1100 0000 ADDR D0 ... DN
CMD
SERIAL READ
SERIAL WRITE
(From 6531)
(From 6531)
(From Host)
(From Host)
PCSZ
PSCK
PSDO
PCSZ
PSCK
PSDO
PSDI
PSDI
Command
ADDR D0 ... DN
x
x
C7
C7
0
0
Figure 3: SPI Slave Port: Typical Read and Write Operations
C6
C6
8 bit CMD
8 bit CMD
C5
C5
HI Z
Table 1: SPI Command Description
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
CMD and ADDR are available to the CPU in IORAM
D0 … DN are ignored.
MPU SPI interrupt is generated
C0
C0
7
7
A15
A15
8
8
A14
A14
16 bit Address
16 bit Address
A1
A1
HI Z
A0
A0
23
23
D7
D7
24
24
x
Description
D6
D6
DATA[ADDR]
DATA[ADDR]
D1
D1
31
31
D0
D0
D7
D7
32
32
Extended Read . . .
Extended Write . . .
DATA[ADDR+1]
D6
DATA[ADDR+1]
D6
DS_6618_005
D1
D1
Rev. 1.3
D0
D0
39
39
x