78m6618-imr/f/p Maxim Integrated Products, Inc., 78m6618-imr/f/p Datasheet - Page 9

• Manufacturer Part Number: 78m6618-imr/f/p
• Description: Octal Power And Energy Measurement Ic
• Manufacturer: Maxim Integrated Products, Inc.

DS_6618_005
1.6
The 78M6618 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of
fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of
the 1-byte instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x
average performance improvement (in terms of MIPS) over the Intel
frequency. See the 78M6618 Programmer’s Reference Manual for more information regarding the
programmability of MPU Memory Organization, Special Function Registers, Interrupts, Counters, and
other CPU controls.
1.6.1 SFR
Several custom Special Function Registers (SFR) registers are implemented in the 78M6618’s 80515
MPU. See the 78M6618 Programmer’s Reference Manual for more information regarding the mapping of
functionality to specific SFR and IORAM addresses.
1.7
The CE and MPU share a single, general purpose 4KB RAM (also referred to as XRAM) for data. The
XRAM is natively accessible as 32bit words from the CE and on 8 bit boundaries from the CPU. The
XRAM is accessed by the CPU through addresses 0x0000 to 0x0FFF.
1.8
The MPU accesses most of its external input and output functionality as well as programmable
functionality through memory mapped IO (IORAM). The IORAM is accessed by the CPU as data
addresses 0x2000 to 0x20FF. See the 78M6618 Programmer’s Reference Manual for more information
regarding the mapping of functionality to specific IORAM addresses.
1.9
The 78M6618 includes 128 KB of on-chip Flash memory. For read/write access from the CPU, the flash
is broken into four 32KB banks that are managed by SFR settings. For erasing of the flash memory from
the CPU the flash is segmented into individual 1024-byte pages and also controlled by SFR settings. See
the 78M6618 Programmer’s Reference Manual for more information regarding the use of flash and the
mapping of functionality to specific SFR settings.
1.9.1 Program Security
The 78M6618 has functionality to guarantee the security of the user’s MPU and CE program code. When
enabled, the security feature limits the ICE to global Flash erase operations only. All other ICE
operations are blocked. Security is enabled by MPU code that is executed in a pre-boot interval before
the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a
global erase of the Flash, followed by a chip reset.
1.10 Oscillator
The 78M6618 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6618 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
The oscillator is powered directly and only from the VBAT pin, which therefore must be connected to a
DC voltage source not to exceed 4 V. The oscillator requires approximately 100 nA, which is negligible
compared to the internal leakage of a battery
Rev. 1.3
80515 MPU Core
XRAM
IORAM
FLASH
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.

8051 device running at the same clock
78M6618 Data Sheet
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