xrt73r06 Exar Corporation, xrt73r06 Datasheet
xrt73r06
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xrt73r06 Summary of contents
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... DECEMBER 2004 GENERAL DESCRIPTION The XRT73R06 is a six channel fully integrated Line Interface Unit (LIU) featuring EXAR’s R (Reconfigurable, Relayless, Redundancy) for E3/ DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel ...
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... XRT73R06 REV. 1.0.0 FEATURES RECEIVER 3 R Technology (Reconfigurable, Redundancy) On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3/DS3/STS-1 Jitter Tolerance Requirement Detects and Clears LOS as per G.775 Receiver Monitor mode handles flat loss with 6 dB cable attenuation ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT F 2. XRT73R06 BGA IGURE IN PACKAGE V ) IEW (See pin list for pin names and function OTTOM XRT73R06 XRT73R06 REV. 1.0 ...
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... Figure 6. Transmit Path Block Diagram .......................................................................................................... 19 3 RANSMIT IGITAL NPUT Figure 7. Typical interface between terminal equipment and the XRT73R06 (dual-rail data) ......................... 19 Figure 8. Transmitter Terminal Input Timing ................................................................................................... 20 Figure 9. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ........................................... 20 3 ............................................................................................................................................ 21 RANSMIT LOCK 3.3 B3ZS/HDB3 E ...
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... Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 44 7.0 Microprocessor interface Block ..................................................................................................... ABLE ELECTING THE ICROPROCESSOR Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 46 7 ICROPROCESSOR NTERFACE T 12: XRT73R06 M ABLE ICROPROCESSOR 7 SYNCHRONOUS AND YNCHRONOUS T 13 ABLE SYNCHRONOUS IMING ................................................................................................................................ 30 (AGC) .................................................................................................................... 31 .......................................................................................................................... 31 ...
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... XRT73R06 REV. 1.0.0 Figure 36. Asynchronous µP Interface Signals During Programmed I/O Read and Write Operations ........... 49 Figure 37. Synchronous µP Interface Signals During Programmed I/O Read and Write Operations ............. ABLE YNCHRONOUS IMING PECIFICATIONS Figure 38. Interrupt process ............................................................................................................................ 51 7.2.1 Hardware Reset: ................................................................................................................................. ABLE EGISTER ...
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... These pins will be active and can control the TTIP and TRING outputs only when the TxON_n bits in the channel register are set . 2. When Transmitters are turned off the TTIP and TRING outputs are Tri- stated. 3. These pins are internally pulled up. 4 XRT73R06 REV. 1.0.0 Transmitter Status OFF OFF OFF ...
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... XRT73R06 REV. 1.0.0 TRANSMIT INTERFACE EAD IGNAL AME YPE F2 TNEG_0 I Transmit Negative Data Input - Channel 0: P2 TNEG_1 Transmit Negative Data Input - Channel 1: G15 TNEG_2 Transmit Negative Data Input - Channel 2: R17 TNEG_3 Transmit Negative Data Input - Channel 3: H3 TNEG_4 Transmit Negative Data Input - Channel 4: ...
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... If configured in Single Rail mode then Line Code Violation will be output. D ESCRIPTION : If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero OTE suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are removed and replaced with ‘0’. 6 XRT73R06 REV. 1.0.0 ...
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... XRT73R06 REV. 1.0.0 RECEIVE INTERFACE EAD IGNAL AME YPE A5 RRING_0 Receive Input - Channel RRING_1 Receive Input - Channel 1: A14 RRING_2 Receive Input - Channel 2: U14 RRING_3 Receive Input - Channel 3: A9 RRING_4 Receive Input - Channel 4: U9 RRING_5 Receive Input - Channel 5: These pins along with RTIP receive the bipolar line signal from the remote DS3/ E3/STS-1 Terminal ...
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... In single frequency mode, this reference clock is not required. OTE : In single frequency mode, this reference clock is not required. OTE : This pin is internally pulled down OTE : OTES 1. The maximum drive capability for the clockouts is 16 mA. 2. This clock out is available both in SFM and non-SFM modes. 8 XRT73R06 REV. 1.0.0 ...
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... XRT73R06 REV. 1.0.0 CONTROL AND ALARM INTERFACE IGNAL AME YPE EAD B7 MRING_0 I Monitor Ring Input - Channel 0: R6 MRING_1 Monitor Ring Input - Channel 1: C14 MRING_2 Monitor Ring Input - Channel 2: R14 MRING_3 Monitor Ring Input - Channel 3: C6 MRING_4 Monitor Ring Input - Channel 4: ...
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... Processor Mode Select: When this pin is tied “High”, the microprocessor is operating in synchronous mode which means that clock must be applied to the PCLK (pin 55). Tie this pin “Low” to select the Asynchronous mode. An internal clock is pro- vided for the microprocessor interface. 10 XRT73R06 REV. 1.0.0 ...
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... XRT73R06 REV. 1.0.0 MICROPROCESSOR INTERFACE EAD IGNAL AME YPE T3 RDY O U3 INT O B4 ADDR[ ADDR[1] B3 ADDR[2] C4 ADDR[3] C3 ADDR[4] C2 ADDR[5] D3 ADDR[6] D4 ADDR[7] N4 D[0] I/O P3 D[1] P4 D[2] P5 D[3] R5 D[4] R4 D[5] R3 D[6] R2 D[7] SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT D ESCRIPTION Ready Acknowledge This pin must be connected to VDD via 3 k ...
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... Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 0 Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 1 Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 2 Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 3 Analog 3.3 V ± 5% VDD - Jitter Attenuator Channel 4 Analog 3.3 V ± 5% VDD - Jitter attenuator Channel 5 Analog GND - Jitter Attenuator Channel 0 12 XRT73R06 REV. 1.0.0 ...
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... XRT73R06 REV. 1.0.0 ANALOG POWER AND GROUND EAD IGNAL AME YPE J4 JaAGND_1 **** F14 JaAGND_2 **** J14 JaAGND_3 **** H4 JaAGND_4 **** H14 JaAGND_5 **** C10 AGND **** R10 AGND **** H9 AGND **** J9 AGND **** K9 AGND **** N15 REFAVDD **** M15 REFGND **** SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT D ESCRIPTION Analog GND - Jitter Attenuator Channel 1 ...
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... Receiver 3.3 V ± 5% VDD - Channel 5 Receiver Digital GND - Channel 0 Receiver Digital GND - Channel 1 Receiver Digital GND - Channel 2 Receiver Digital GND - Channel 3 Receiver Digital GND - Channel 4 Receiver Digital GND - Channel 5 VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% VDD 3.3 V ± 5% Digital GND Digital GND 14 XRT73R06 REV. 1.0.0 ...
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... XRT73R06 REV. 1.0.0 DIGITAL POWER AND GROUND EAD IGNAL AME YPE M14 JaDGND_2 **** M4 JaDGND_1 **** P7 DGND **** H8 DGND **** J8 DGND **** K8 DGND **** H10 DGND **** J10 DGND **** K10 DGND **** SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT D ESCRIPTION Digital GND Digital GND Digital GND Digital GND Digital GND ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FUNCTIONAL DESCRIPTION The XRT73R06 is a six channel fully integrated Line Interface Unit featuring EXAR’s R (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel can be independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of 12 ...
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... XRT73R06 REV. 1.0.0 2.0 CLOCK SYNTHESIZER The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1 and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin " ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 18 XRT73R06 REV. 1.0.0 ...
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... Terminal Equipment (E3/DS3 or STS-1 Framer) SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT IAGRAM Tx Jitter Timing Pulse MUX Attenuator Control Tx Control XRT73R06 ( TPData Transmit TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU 19 áç áç áç áç ...
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... IGURE INGLE AIL OR ATA Data TPData TxClk RANSMITTER ERMINAL NPUT t FTX t t TSU THO ORMAT NCODER AND ECODER ARE XRT73R06 REV. 1.0.0 IMING MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz NABLED 0 ...
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... XRT73R06 REV. 1.0 IGURE UAL AIL ATA ORMAT Data TPData TNData TxClk 3.2 Transmit Clock The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit ...
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... DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit load as shown in Figure 13 EST IRCUIT R1 TTIP(n) TPData(n) 31.6 +1% TNData(n) R2 TxClk(n) TRing(n) 31 XRT73R06 REV. 1.0 1:1 ...
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... XRT73R06 REV. 1.0.0 3.5 E3 line side parameters The XRT73R06 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 22 IGURE ULSE V = 100% 50% 10% 0% 10% SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT E3 (34 ...
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... Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time N : The above values are OTE RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0 C and V = 3.3 V± 5 XRT73R06 REV. 1.0.0 MIN TYP MAX UNITS 0.90 1.00 1. 0.95 1.00 1.05 12 ...
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... XRT73R06 REV. 1.0.0 F 15. B GR-253 CORE T IGURE ELLCORE 1.2 1 0.8 0.6 0.4 0 IME IN NIT NTERVALS < < -0.85 T -0.38 < < -0.38 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.26 < < 0.26 T 1.4 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT RANSMIT UTPUT ULSE EMPLATE FOR Tim ...
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... IDE UTPUT AND ECEIVER INE 0.65 0.90 0.90 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V ± 5 DS3 B EMPLATE FOR AS PER ELLCORE XRT73R06 REV. 1.0 (GR-253) IDE NPUT PECIFICATIONS NITS 0.75 0. 1.00 1.10 ...
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... XRT73R06 REV. 1.0 IME IN NIT NTERVALS < < -0.85 T -0.36 < < -0.36 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.36 < < 0. DS3 T L ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) ...
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... To permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control to TxON pin TTIP(n) TRing(n) TPData(n) TNData(n) R1 TxClk(n) MTIP(n) 270 R2 MRing(n) 270 28 XRT73R06 REV. 1.0.0 R1 31.6 + 1:1 31 ...
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... XRT73R06 REV. 1.0.0 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 29 áç áç áç áç ...
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... Whether using E3, DS-3 or STS-1, the LIU requires the same bill of materials, see Figure 19 IGURE ECEIVE INE NTERFACE DS-3/E3/STS-1 IAGRAM Clock & Data Jitter MUX Recovery Attenuator LOS Detector C ONNECTION 1:1 Receiver 37.5 37.5 0.01 F RLOS_n 30 XRT73R06 REV. 1.0.0 RxClk_n HDB3/ B3ZS RxPOS_n Decoder RxNEG/LCV_n RLOS_n Channel n RTIP_n 75 RRing_n ...
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... XRT73R06 REV. 1.0.0 4.2 Adaptive Gain Control (AGC) The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak detector provides feedback to the equalizer before slicing occurs. ...
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... AND PPLICATIONS IGNAL EVEL TO ECLARE ETTING D EFECT 0 < 75mVpk 0 < 45mVpk 1 < 120mVpk 1 < 55mVpk 0 < 120mVpk 0 < 50mVpk 1 < 125mVpk 1 < 55mVpk 32 XRT73R06 REV. 1.0.0 ) ALOS ALOS IGNAL EVEL TO LEAR D EFECT > 130mVpk > 60mVpk > 45mVpk > 180mVpk > 170mVpk > 75mVpk > 205mVpk > 90mVpk ...
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... XRT73R06 REV. 1.0.0 4.5.3 E3 LOS Condition: If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No transitions is defined as a signal level between 15 and 35 dB below the normal. This is illustrated in Figure 21. ...
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... PRBS F 24 IGURE NTERFERENCE ARGIN Sine Wave N Generator 17.184mHz Signal Source PRBS T S DS3/STS-1 EST ET UP FOR Attenuator Cable Simulator T S E3. EST ET UP FOR Attenuator 1 Attenuator 2 Cable Simulator 34 XRT73R06 REV. 1.0.0 DUT XRT75R06 Test Equipment DUT XRT75R06 Test Equipment ...
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... XRT73R06 REV. 1.0.0 T ABLE M C ODE ABLE E3 DS3 STS-1 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT NTERFERENCE ARGIN EST ESULTS ENGTH TTENUATION NTERFERENCE feet 225 feet 450 feet 0 feet 225 feet 450 feet 35 áç áç áç ...
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... B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output pins to indicate line code violation. D ECEIVER ATA OUTPUT AND CODE VIOLATION TIMING t RRX FRX t LCVO 36 XRT73R06 REV. 1.0.0 MIN TYP MAX UNITS 34.368 MHz 44 ...
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... Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 27 shows the jitter tolerance curve as per GR-499 specification. SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT Data DUT XRT73R06 Clock 37 áç áç áç ...
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... E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude versus the modulation frequency for various standards. F DS3/STS 0 JITTER FREQUENCY (kHz) 38 XRT73R06 REV. 1.0.0 GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT73R06 20 100 ITU-T G.823 XRT73R06 800 ...
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... XRT73R06 REV. 1.0 ABLE ITTER MPLITUDE VERSUS I J NPUT ATE S TANDARD ( / ) 34368 ITU-T G.823 1.5 44736 GR-499 5 CORE Cat I 44736 GR-499 10 CORE Cat II 51840 GR-253 15 CORE Cat II 5 ITTER RANSFER Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency ...
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... Since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies ITTER TTENUATOR ERFORMANCE XRT73R06 REV. 1.0.0 ...
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... Any subsequent single bit error insertion must be done by first writing a “0” to INSPRBS bit and followed by a “1”. Figure 30 shows the status of RNEG/LCV pin when the XRT73R06 is configured in PRBS mode PRBS mode, the device is forced to operate in Single-Rail Mode. ...
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... SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 6.2 LOOPBACKS The XRT73R06 offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 6.2.1 ANALOG LOOPBACK In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs RTIP_n and RRing_n as shown in Figure 31 ...
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... XRT73R06 REV. 1.0.0 6.2.2 DIGITAL LOOPBACK When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 32 IGURE IGITAL OOPBACK TxCLK HDB3/B3ZS ...
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... Figure 34. TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode (TAOS) IGURE RANSMIT LL NES TxCLK HDB3/B3ZS TxPOS ENCODER TxNEG RxCLK HDB3/B3ZS RxPOS DECODER RxNEG TIMING Tx CONTROL TAOS DATA & CLOCK Rx RECOVERY 44 XRT73R06 REV. 1.0.0 TTIP Transmit All 1's TRing RTIP RRing ...
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... XRT73R06 REV. 1.0.0 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 45 áç áç áç áç ...
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... MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT73R06 supports a parallel interface asynchronously or synchronously timed to the LIU. The mi- croprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 11 ...
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... Read/Write access Chip Select Input This active low signal selects the microprocessor interface of the XRT73R06 LIU and enables Read/Write operations with the on-chip register locations Read Signal This active low input functions as the read signal from the local pin is pulled “ ...
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... After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the µP that the data has been written into the internal register location, and that it is ready for the next command. 6. The CS input pin must be pulled "High" before a new command can be issued. D ESCRIPTION 48 XRT73R06 REV. 1.0.0 input pin WR ...
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... XRT73R06 REV. 1.0.0 F 36. A µP I IGURE SYNCHRONOUS NTERFACE READ OPERATION t 0 Addr[7:0] Valid Address CS D[7: RDY T ABLE S P YMBOL ARAMETER t Valid Address to CS Falling Edge Falling Edge to RD Assert Assert to RDY Assert Pulse Width ( Falling Edge to WR Assert ...
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... Valid Data for Readback YNCHRONOUS IMING PECIFICATIONS 5ns period 50 XRT73R06 REV. 1.0.0 I EAD AND RITE PERATIONS WRITE OPERATION Valid Address Data Available to Write Into the LIU NITS - ns, see note 1 - ...
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... XRT73R06 REV. 1.0.0 F 38. I IGURE NTERRUPT PROCESS YES SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ERROR CONDITION OCCURS Interrupt enable NO bits at 0x60 and 0xn1 set? YES Interrupt status bits at 0x61 and 0xn2 set. Interrupt Generated INT pin goes "Low" Interrupt Service Routine reads the status ...
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... EGISTER AP AND IT AMES D B ATA TxON_5 TxON_4 TxON_3 RxON_5 RxON_4 RxON_3 INTEN_5 INTEN_4 INTEN_3 INTEN_2 INTEN_1 INTEN_0 INTST_5 INTST_4 INTST_3 INTST_2 INTST_1 INTST_0 Reserved Chip version number 52 XRT73R06 REV. 1.0.0 ITS TxON_2 TxON-1 TxON_0 RxON_2 RxON_1 RxON_0 ...
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... XRT73R06 REV. 1.0.0 T ABLE A R DDRESS EGISTER T YPE ( AME 0x00 R/W APS # 1 0x08 R/W APS # 2 0x60 R/W Interrupt Enable 0x61 ROR Interrupt Status 0x62 - 0x6D 0x6E R Device _ id 0x6F R Version Chip_version This read only register contains chip version number Number T 17 ABLE EGISTER ...
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... TxMON_n INSPRBS Reserved _n DLOSDIS ALOSDIS RxCLKIN _n _n PRBSEN_ RLB_n LLB_n N_n 0 Reserved Reserved Reserved Reserved Reserved Reserved Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit 4 54 XRT73R06 REV. 1.0 0,1,2,3,4, RLOL_n RLOS_n DMO_n TAOS_n TxCLKINV TxLEV_n _n LOSMUT_ RxMON_n REQEN_ V_n n n E3_n STS1/ ...
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... XRT73R06 REV. 1.0.0 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME D0 D1 0x01 (ch 0) R/W Interrupt 0x11 (ch 1) Enable 0x21 (ch 2) (source D2 0x31 (ch 3) level) 0x41 (ch 4) 0x51 ( D6- 0x02 (ch 0) Reset Interrupt 0x12 ( Status D2 0x22 (ch 2) Read (source 0x32 (ch 3) ...
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... DS/STS-1 applications. PRBSLS_n This bit is set when the PRBS detector has been enabled and it is not in sync with the incoming data pattern. Once the sync is achieved, it will be cleared. Reserved 56 XRT73R06 REV. 1.0.0 HANNEL N D EFAULT V ALUE ...
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... XRT73R06 REV. 1.0.0 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME D0 D1 0x04 (ch 0) R/W Transmit D2 0x14 (ch 1) Control 0x24 (ch 2) 0x34 (ch 3) 0x44 ( 0x54 ( D7- 0x05 (ch 0) R/W Receive 0x15 (ch 1) Control 0x25 (ch 2) 0x35 ( 0x45 (ch 4) 0x55 (ch 5) ...
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... RCLK to generate TCLK will cause an unstable condition and should be avoided. CLKOUTE Set this bit to enable the CLKOUTs on a per channel N_n basis. The frequency of the output clock is depen- dent on the configuration of the channels, either E3, DS3 or STS-1. Reserved 58 XRT73R06 REV. 1.0.0 HANNEL N D EFAULT V ALUE ...
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... XRT73R06 REV. 1.0.0 T ABLE A R DDRESS EGISTER T BIT# YPE ( AME 0x07 (ch 0) R/W Jitter D7-D5 0x17 (ch 1) Attenuator 0x27 (ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 (ch 5) SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 18 EGISTER AP ESCRIPTION S D YMBOL ESCRIPTION Reserved This bit is Reserved. ...
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... ATINGS MIN MAX -0.5 6.0 -0.5 5.5 100 -65 150 - 2000 20 LECTRICAL HARACTERISTICS ARAMETER = XRT73R06 REV. 1.0.0 UNITS COMMENTS V Note 1 V Note 1 mA Note 1 0 Note linear airflow 0 ft./min C 0 linear air flow 0ft/min C/W (See Note 3 below) level EIA/JEDEC JESD22-A112-A ...
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... XRT73R06 REV. 1.0.0 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 61 áç áç áç áç ...
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... APPENDIX A 21: TRANSFORMER RECOMMENDATIONS T 22 ABLE RANSFORMER ETAILS V I ENDOR NSULATION PULSE 3000 V PULSE 1500 V PULSE 1500 V PULSE 1500 V HALO 1500 V 1500 V 62 XRT73R06 REV. 1.0.0 V ALUE 1 1500 Vrms 0 ACKAGE YPE Large Thru-hole Small Thru-hole SMT SMT SMT SMT ...
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... XRT73R06 REV. 1.0.0 Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 Website: http://www.pulseeng.com Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165 Email: info@haloelectronics.com Website: http://www.haloelectronics.com Transpower Technologies, Inc. Corporate Office Park Center West Building ...
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... INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.067 0.098 1.70 2.50 A1 0.016 0.028 0.40 0.70 A2 0.012 0.024 0.30 0.60 A3 0.039 0.047 1.00 1.20 D 0.898 0.913 22.80 23.20 D1 0.800 BSC 20.32 BSC D2 0.780 0.795 19.80 20.20 b 0.024 0.035 0.60 0.90 e 0.050 BSC 1.27 BSC 10° 20° 10° 20° 64 XRT73R06 REV. 1.0 PERATING EMPERATURE ANGE ° ° ...
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... XRT73R06 REV. 1.0.0 REVISIONS R D EVISION ATE P1.0.0 07/15/04 First release of the preliminary datasheet. 1.0.0 12/16/04 Release to production. Added Power Dissapation and Power Supply Current to electrical. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...