wm8903 Wolfson Microelectronics plc, wm8903 Datasheet
wm8903
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wm8903 Summary of contents
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... Ultra Low Power CODEC for Portable Audio Applications DESCRIPTION The WM8903 is a high performance ultra-low power stereo CODEC optimised for portable audio applications. The device features stereo ground-referenced headphone amplifiers using the Wolfson ‘Class-W’ amplifier techniques - incorporating an innovative dual-mode charge pump architecture - to optimise efficiency and power consumption during playback ...
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... WM8903 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ......................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ...................................................................... 7 TERMINOLOGY ............................................................................................................ 7 COMMON TEST CONDITIONS .................................................................................... 7 INPUT SIGNAL PATH ................................................................................................... 8 OUTPUT SIGNAL PATH ............................................................................................. 10 BYPASS PATH ............................................................................................................ 12 CHARGE PUMP .......................................................................................................... 13 OTHER PARAMETERS .............................................................................................. 13 POWER CONSUMPTION .................................................................................... 14 COMMON TEST CONDITIONS .................................................................................. 14 POWER CONSUMPTION MEASUREMENTS ...
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... POWER-ON RESET ................................................................................................. 109 QUICK START-UP AND SHUTDOWN ...................................................................... 111 CHIP RESET AND DEVICE ID .................................................................................. 112 REGISTER MAP ................................................................................................. 113 REGISTER BITS BY ADDRESS ............................................................................... 117 APPLICATIONS INFORMATION ....................................................................... 153 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 153 MIC DETECTION SEQUENCE USING MICBIAS CURRENT .................................... 154 IMPORTANT NOTICE ........................................................................................ 158 ADDRESS ................................................................................................................. 158 w WM8903 PP, Rev 3.1, August 2009 3 ...
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... WM8903 PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8903LGEFK/V -40°C to +85°C WM8903LGEFK/RV -40°C to +85°C Note: Tube quantity = 95 Reel quantity = 3,500 w PACKAGE SENSITIVITY LEVEL 40-lead QFN (5x5x0.55mm, lead-free) 40-lead QFN (5x5x0.55mm, lead-free, tape and reel) Pre-Production MOISTURE PEAK SOLDERING TEMPERATURE MSL3 260° ...
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... Left channel input 3 Left channel input 2 Left channel input 1 Control interface data Input / 2-wire acknowledge output Control interface clock Input GPIO3 / control interface address selection Digital core supply Digital buffer supply (powers audio interface and control interface) WM8903 PP, Rev 3.1, August 2009 5 ...
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... All digital and analogue supplies are completely independent from each other; there is no restriction on power supply sequencing. 3. HPOUTL, HPOUTR, LINEOUTL, LINEOUTR are outputs, and should not normally become connected to DC levels. However, if the limits above are exceeded, then damage to the WM8903 may occur. RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range (Core) ...
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... Unless otherwise stated, the following test conditions apply throughout the following sections: • DCVDD = 1.2V • DBVDD = 1.8V • AVDD = CPVDD =1.8V • Ambient temperature = +25°C • Audio signal: 1kHz sine wave, sampled at 48kHz with 24-bit data resolution Additional, specific test conditions are given within the relevant sections below. w WM8903 PP, Rev 3.1, August 2009 7 ...
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... WM8903 INPUT SIGNAL PATH Single-ended stereo line record - IN1L+IN1R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 00000b (-1.5dB) Total signal path gain = 4.45dB, incorporating 6dB single-ended to differential conversion gain PARAMETER Full Scale Input Signal Level (for ADC 0dBFS) ...
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... At ADC output with ADC_HPF_ENA=0 SNR A-weighted THD -31dBV input THD+N -31dBV input CMRR 1kHz, 100mVpk-pk 1kHz signal, -31dBV 10kHz signal, -31dBV 1kHz signal, -31dBV PSRR 1kHz, 100mVpk-pk 20kHz, 100mV pk-pk WM8903 MIN TYP MAX 0.019 -34.3 0.055 11864 LSBs (24-bit) 47 LSBs (16-bit) 73 -78 ...
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... WM8903 PGA and microphone boost PARAMETER Minimum PGA gain setting Maximum PGA gain setting Single-ended to differential conversion gain PGA gain accuracy Mute attenuation Equivalent input noise OUTPUT SIGNAL PATH Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 15Ω load Test conditions: HPOUTL_VOL = HPOUTR_VOL = 111001b (0dB) ...
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... Measured Differentially SNR A-weighted THD THD+N 1kHz signal, 0dBFS 10kHz signal, 0dBFS 1kHz signal PSRR 1kHz, 100mVpk-pk 20kHz, 100mV pk-pk TEST CONDITIONS MIN +6dB to 0dB -1.5 0dB to -57dB -1 HPOUTL/R LINEOUTL/R Differential LINE (LOP-LOR/ROP-RON) WM8903 MIN TYP MAX UNIT 0.95 1.0 1.05 Vrms -0.446 0 0.424 dBV 2.69 2.83 2.97 Vpk-pk 0 +/-1 ...
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... WM8903 BYPASS PATH Pseudo-differential stereo line input to stereo line output- IN2L-IN3L / IN2R-IN3R pins to LINEOUTL+LINEOUTR pins with 3.01kΩ / 50pF load Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 01111b (+4.2dB) LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) Total signal path gain = +4.20dB PARAMETER ...
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... MAX TYP MAX AVDD/2 +3% MIN TYP MAX -5% 0.9×AVDD + 100 15 1.25-15 400 520 647 50 40 250 TYP MAX 0.3×DBVDD 0.1×DBVDD PP, Rev 3.1, August 2009 WM8903 UNIT μs μF μF μF UNIT V UNIT V mA nV/√Hz dB μA ms μ UNIT ...
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... WM8903 POWER CONSUMPTION The WM8903 power consumption is dependent on many parameters. Most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. The power consumption on each supply rail varies approximately with the square of the voltage. Power consumption is greater at fast sample rates than at slower ones. When the digital audio interface is operating in Master mode, the DBVDD current is significantly greater than in Slave mode ...
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... V 1.8 1.60 1.2 0.76 1.8 1.8 1.60 1.2 0.76 1.8 1.8 1.60 1.2 0.90 1.8 1.8 1.60 1.2 0.92 1.8 1.8 1.60 1.2 0.65 1.8 1.8 1.60 1.2 0.71 1.8 AVDD DCVDD 1.8 1.95 1.2 0.76 1.8 1.8 1.95 1.2 0.68 1.8 AVDD DCVDD 1.8 1.46 1.2 0.12 1.8 1.8 1.46 1.2 0.12 1.8 AVDD DCVDD 1.8 0.01 1.2 0.012 1.8 WM8903 DBVDD CPVDD TOTAL 0.00 1.8 0.41 4.5 0.09 1.8 0.41 4.7 0.09 1.8 1.85 7.5 0.09 1.8 5.77 14.5 0.03 1.8 0.41 4.4 0.03 1.8 1.85 7.1 DBVDD CPVDD TOTAL 0.09 1.8 0.32 5.2 0.03 1.8 0.32 4.9 DBVDD CPVDD TOTAL 0.00 1.8 1.54 5.5 0.00 1.8 4.54 11.0 DBVDD CPVDD TOTAL 0.003 1.8 0.005 0.047 PP, Rev 3.1, August 2009 15 ...
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... WM8903 SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: • • • • Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK Figure 1 Master Clock Timing Master Clock Timing ...
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... LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge w SYMBOL MIN TYP DDA t 10 DST t 10 DHT WM8903 MAX UNIT PP, Rev 3.1, August 2009 17 ...
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... WM8903 SLAVE MODE Figure 3 Audio Interface Timing – Slave Mode Audio Interface Timing – Slave Mode PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time from BCLK rising edge ...
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... Pre-Production TDM MODE In TDM mode important that two devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8903 ADCDAT pin tri-stating at the start and end of the data transmission is described below. Figure 4 Audio Interface Timing – TDM Mode Audio Interface Timing – TDM Mode ...
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... WM8903 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 Attenuation Stopband 3 Stopband 3 Attenuation DAC FILTERS ...
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... DAC_SB_FILT = 0b (Normal Filter) Sample Rate > 24kHz (except 88.2kHz) w Figure 7 DAC Filter Response for CLK_SYS_MODE = 00b or 01b DAC_SB_FILT = 1b (Sloping StopBand Filter) Sample Rate ≤ 24kHz Figure 9 DAC Filter Response for CLK_SYS_MODE = 00b or 01b DAC_SB_FILT = 0b (Normal Filter) Sample Rate > 24kHz PP, Rev 3.1, August 2009 WM8903 21 ...
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... WM8903 Figure 10 DAC Filter Response for CLK_SYS_MODE = 01b (Clock is 272 x fs related) DAC_SB_FILT = 0b (Normal Filter) Sample Rate = 88.2kHz ADC FILTER RESPONSES Figure 11 ADC Filter Response for CLK_SYS_MODE = 10b (not applicable to 88.2/96kHz) w Figure 12 ADC Filter Response for CLK_SYS_MODE = 00b or 01b PP, Rev 3.1, August 2009 ...
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... MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) Figure 15 ADC Digital High Pass Filter Ripple (48kHz, Voice Mode, ADC_HPF_CUT=01, 10 and 11) WM8903 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k hpf_response2.res MAGNITUDE(dB) PP, Rev 3.1, August 2009 7.9761k 20.039k 23 ...
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... WM8903 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 16 De-Emphasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - -10 Frequency (Hz) Figure 18 De-Emphasis Digital Filter Response (44.1kHz) MAGNITUDE(dB 5000 10000 ...
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... DEVICE DESCRIPTION ANALOGUE INPUT SIGNAL PATH The WM8903 has six analogue input pins, which may be used to support connections to multiple microphone or line input sources. The input multiplexer on the Left and Right channels can be used to select different configurations for each of the input sources. The analogue input paths can support line and microphone inputs, in single-ended, pseudo-differential and fully-differential modes ...
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... WM8903 INPUT PGA ENABLE The input PGAs (Programmable Gain Amplifiers) and Multiplexers are enabled using register bits INL_ENA and INR_ENA, as shown in Table 1. REGISTER ADDRESS R12 (0Ch) Power Management 0 Table 1 Input PGA Enable To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled. ...
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... L_MODE [1:0] 00 5:4 R_IP_SEL_N 00 [1:0] 3:2 R_IP_SEL_P 01 [1:0] 1:0 R_MODE [1:0] 00 WM8903 DESCRIPTION Selects input for inverting side of left input path IN1L 01 = IN2L 1X = IN3L Selects input for non-inverting side of left input path IN1L 01 = IN2L 1X = IN3L Sets the mode for the left analogue input Single-Ended 01 = Differential Line 10 = Differential MIC ...
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... WM8903 SINGLE-ENDED INPUT The Single-Ended PGA configuration is illustrated in Figure 23 for the Left channel. The available gain in this mode is from -1.57dB to +28.5dB in non-linear steps. The input impedance is 12kΩ. The input to the ADC is phase inverted with respect to the selected input pin. Different input pins can be selected in the same mode by altering the L_IP_SEL_N field. The equivalent configuration is also available on the Right channel ...
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... Differential Mic Mode, as the PGA will not function correctly under this setting. In single- ended mode (L_MODE / R_MODE = 00b), the conversion from single-ended to differential within the WM8903 adds a further 6dB of gain to the signal path. Each input channel can be independently muted using LINMUTE and RINMUTE. ...
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... WM8903 LIN_VOL[4:0], RIN_VOL[4:0] Table 4 Input PGA Volume Range w GAIN – PGA MODE = 00000 -1.5 dB 00001 -1.3 dB 00010 -1.0 dB 00011 -0.7 dB 00100 -0.3 dB 00101 0.0 dB 00110 +0.3 dB 00111 +0.7 dB 01000 +1.0 dB 01001 +1.4 dB 01010 +1.8 dB 01011 +2.3 dB 01100 +2.7 dB 01101 +3.2 dB 01110 +3.7 dB 01111 +4.2 dB 10000 +4.8 dB 10001 +5.4 dB 10010 +6.0 dB 10011 +6.7 dB 10100 +7.5 dB 10101 +8.3 dB 10110 +9.2 dB 10111 +10.2 dB 11000 +11.4 dB 11001 +12.7 dB 11010 +14.3 dB 11011 +16 ...
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... Right Input 1 Table 5 Common Mode Amplifier Enable w BIT LABEL DEFAULT 6 INL_CM_ENA 1 6 INR_CM_ENA 1 WM8903 DESCRIPTION Left Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for L_MODE=01 – Differential Line) Right Input PGA Common Mode Rejection enable 0 = Disabled 1 = Enabled (only available for R_MODE=01 – ...
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... ELECTRET CONDENSER MICROPHONE INTERFACE Electret Condenser microphones may be connected as single-ended or differential inputs to the Input PGAs described in the “Analogue Input Signal Path” section. The WM8903 provides a low-noise reference voltage suitable for biasing electret condenser microphones. This is provided on the MICBIAS pin, and can be enabled using the MICBIAS_ENA register bit. ...
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... MCLK to be present CLK_SYS_ENA = 1 WSMD_CLK_ENA = 1 (1) insertion event happens at any time during this period MCLK IRQ GPIO WM8903 before the signal DET (2) insertion indicated t DET after MCLK re-started t DET PP, Rev 3.1, August 2009 33 ...
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... WM8903 MICROPHONE HOOK SWITCH DETECTION In a typical application, microphone hook switch operation would be detected when the MICBIAS current exceeds the Short Circuit Detect threshold set by MICSHORT_THR. In order to generate a MICBIAS Short Circuit Detect interrupt from this event, MICSHRT_INV must be cleared to 0 (see “ ...
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... The digital microphone interface requires that MIC1 transmits a data bit each time that DMIC_LR is high, and MIC2 transmits when DMIC_LR is low. The WM8903 samples the digital microphone data in the middle of each DMIC_LR clock phase. Each microphone must tri-state its data output when the other microphone is transmitting ...
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... WM8903 Figure 29 Digital Microphone Interface Timing The digital microphone interface control fields are described in Table 7. REGISTER ADDRESS R164 (A4h) Clock Rate Test 4 Table 7 Digital Microphone Interface Control In addition to setting the ADC_DIG_MIC bit as described in Table 7, the pins GPIO1/DMIC_LR and GPIO2/DMIC_DAT must also be configured to provide the digital microphone interface function. See “ ...
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... Pre-Production ANALOGUE-TO-DIGITAL CONVERTER (ADC) The WM8903 uses two 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is proportional to AVDD. See “Electrical Characteristics” section for further details ...
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... WM8903 ADCL_VOL or ADCR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 11h -65.625 12h -65.250 13h -64.875 14h -64.500 15h -64.125 16h -63.750 17h -63.375 18h -63.000 19h -62.625 1Ah -62 ...
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... WM8903 (e.g. ADC_HPF_CUT=11 at DEFAULT DESCRIPTION 00 ADC Digital High Pass Filter Cut- Off Frequency (fc Hi-fi mode (fc=4Hz at fs=48kHz Voice mode 1 (fc=127Hz at fs=16kHz Voice mode 2 (fc=130Hz at fs=8kHz Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate fs. ...
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... WM8903 ADC OVERSAMPLING RATIO (OSR) The ADC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is high for best performance; using the lower OSR setting reduces ADC power consumption. REGISTER ADDRESS R10 (0Ah) Analogue ADC 0 Table 13 ADC Oversampling Ratio Note that the Low Power (64 x fs) oversampling option is not supported when CLK_SYS_MODE=10 (see “ ...
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... The “knee” in Figure 30 is represented by T and Y, which are determined by register fields DRC_THRESH_COMP and DRC_AMP_COMP respectively. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from the other parameters, using the equation The DRC Compression parameters are defined in Table 15. w WM8903 PP, Rev 3.1, August 2009 41 ...
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... WM8903 REGISTER ADDRESS R42 (2Ah) DRC 2 R43 (2Bh) DRC 3 Table 15 DRC Compression Control GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and DRC_MAXGAIN. These limits can be used to alter the DRC response from that illustrated in Figure 30 ...
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... DRC_MAXGAIN 01 [1:0] BIT LABEL DEFAULT 15:12 DRC_ATTACK_ 0011 RATE [3:0] 11:8 DRC_DECAY_R 0010 ATE [3:0] WM8903 DESCRIPTION Minimum gain the DRC can use to attenuate audio signals 00 = 0dB (default -6dB 10 = -12dB 11 = -18dB Maximum gain the DRC can use to boost audio signals 00 = 12dB 01 = 18dB (default 24dB 11 = 36dB DESCRIPTION ...
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... WM8903 ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP_ENA bit ...
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... DRC_RATE_QR 00 [1:0] BIT LABEL DEFAULT 12:11 DRC_THRESH_ 01 HYST [1:0] 3 DRC_SMOOTH 1 _ENA 0 DRC_HYST_EN 1 A WM8903 DESCRIPTION Quick release enable 0 = disabled 1 = enabled Quick release crest factor threshold 00 = 12dB 01 = 18dB (default 24dB 11 = 30dB Quick release decay rate (seconds/6dB 0.725ms (default 1.45ms 10 = 5.8ms 11 = Reserved DESCRIPTION Gain smoothing hysteresis ...
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... In addition, data from either of the digital audio interface channels can be routed to either the left or the right DAC. See “Digital Audio Interface” for more information on the audio interface. DIGITAL MIXING PATHS Figure 31 shows the digital mixing paths available in the WM8903 digital core. w BIT LABEL ...
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... The input data source for each DAC can be changed under software control using register bits DACL_SRC and DACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DACR_DATINV. These register bits are described in Table 22. w WM8903 PP, Rev 3.1, August 2009 47 ...
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... WM8903 REGISTER ADDRESS R24 (18h) Audio Interface 0 R38 (26h) ADC Digital 0 Table 22 Digital Mixing Control w BIT LABEL DEFAULT 12 DACL_DATINV 0 11 DACR_DATINV 0 AIFADCL_SRC AIFADCR_SRC 1 5 AIFDACL_SRC 0 4 AIFDACR_SRC 1 1 ADCL_DATINV 0 0 ADCR_DATINV 0 Pre-Production DESCRIPTION Left DAC Invert 0 = Left DAC output not inverted ...
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... ADCR_DAC_SV 0000 OL [3:0] 3:2 ADC_TO_DACL 00 [1:0] ADC_TO_DACR 1:0 00 [1:0] WM8903 DESCRIPTION DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS +12dB (Input data must not exceed -12dBFS +18dB (Input data must not exceed -18dBFS) DESCRIPTION Left Digital Sidetone Volume (See Table 25 for volume range) ...
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... WM8903 ADCL_DAC_SVOL or ADCR_DAC_SVOL Table 25 Digital Sidetone Volume SIDETONE VOLUME 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0 Pre-Production PP, Rev 3.1, August 2009 50 ...
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... Pre-Production DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8903 DACs receive digital input data from the DACDAT pin and via the digital sidetone path (see “Digital Mixing” section). The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The Wolfson SmartDAC™ ...
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... WM8903 DACL_VOL or DACR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 11h -65.625 12h -65.250 13h -64.875 14h -64.500 15h -64.125 16h -63.750 17h -63.375 18h -63.000 19h -62.625 1Ah -62 ...
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... Pre-Production DAC SOFT MUTE AND SOFT UN-MUTE The WM8903 has a soft mute function. When enabled, this gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_MUTEMODE register bit ...
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... WM8903 DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on whichever DAC is enabled. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. Only one DAC must be enabled in order to use this function. ...
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... DACBIAS_SEL 00 2:1 DACVMID_BIAS_ 00 SEL BIT LABEL DEFAULT 0 DAC_OSR 0 WM8903 DESCRIPTION DAC Bias boost 0 = Disable 1 = Enable When DAC Bias boost is enabled, the bias selected by DACBIAS_SEL and DACVMID_BIAS_SEL are both doubled. DAC bias current select 00 = Normal bias 01 = Normal bias x 0 Normal bias x 0. Normal bias x 0.75 ...
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... WM8903 OUTPUT SIGNAL PATH The WM8903 has one pair of analogue mixers (the “left” and right” mixers) feeding the headphone outputs HPOUTL and HPOUTR as well as the line outputs LINEOUTL and LINEOUTR, and a separate pair of mixers (the “speaker mixers”) feeding the differential line outputs LON/LOP and RON/ROP (these pins are in the “ ...
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... LINEOUTR_PGA 0 _ENA MIXSPKL_ENA 1 0 MIXSPKR_ENA SPKL_ENA 0 0 SPKR_ENA 0 WM8903 DESCRIPTION Left Output Mixer Enable 0 = disabled 1 = enabled Right Output Mixer Enable 0 = disabled 1 = enabled Left Headphone Output Enable 0 = disabled 1 = enabled Right Headphone Output Enable 0 = disabled 1 = enabled Left Line Output Enable 0 = disabled 1 = enabled ...
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... WM8903 OUTPUT PGA BIAS CONTROL The output PGA circuits use the Master bias current (see “Reference Voltages and Master Bias”). The output PGA bias currents can also be controlled using the PGA_BIAS field as described in Table 36. Selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes ...
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... DACL_TO_MIXO 0 UTR DACR_TO_MIXO 2 1 UTR 1 BYPASSL_TO_MI 0 XOUTR 0 BYPASSR_TO_M 0 IXOUTR WM8903 DESCRIPTION Left DAC to Left Output Mixer Enable 0 = disabled 1 = enabled Right DAC to Left Output Mixer Enable 0 = disabled 1 = enabled Left Analogue Input to Left Output Mixer Enable 0 = disabled 1 = enabled Right Analogue Input to Left Output ...
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... WM8903 The input signals to the speaker mixers are enabled and controlled using the register fields described in Table 39. These mixers provide a selectable 0dB or -6dB volume control on each input. The input signals may also be controlled at source using the control fields LIN_VOL, RIN_VOL, DACL_VOL and DACR_VOL, but it should be noted that adjusting these fields would also affect the other output mixers ...
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... VOL 2 DACR_MIXSPKR 0 _VOL 1 BYPASSL_MIXSP 0 KR_VOL 0 BYPASSR_MIXS 0 PKR_VOL WM8903 DESCRIPTION Left DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB Right DAC to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB Left Analogue Input to Right Spkr Mixer volume control 0 = 0dB 1 = -6dB Right Analogue Input to Right Spkr ...
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... WM8903 REGISTER ADDRESS R57 (39h) Analogue OUT1 Left R58 (3Ah) Analogue OUT1 Right Table 40 Volume Control for HPOUTL and HPOUTR w BIT LABEL DEFAULT 8 HPL_MUTE 0 7 HPOUTVU 0 HPOUTLZC 6 0 5:0 HPOUTL_VOL 10_1101 [5:0] HPR_MUTE HPOUTVU 0 6 HPOUTRZC 0 5:0 HPOUTR_VOL 10_1101 [5:0] Pre-Production DESCRIPTION Left Headphone Output Mute ...
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... E 7 LINEOUTVU 0 6 LINEOUTRZC 0 5:0 LINEOUTR_VOL 11_1001 [5:0] WM8903 DESCRIPTION Left Line Output Mute 0 = Un-mute 1 = Mute Line Output Volume Update Writing this bit will update LINEOUTL and LINEOUTR volumes simultaneously. Left Line Output Zero Cross Enable 0 = disabled 1 = enabled Left Line Output Volume ...
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... WM8903 REGISTER ADDRESS R62 (3Eh) Analogue OUT3 Left R63 (3Fh) Analogue OUT3 Right Table 42 Volume Control for LON/LOP and RON/ROP w BIT LABEL DEFAULT 8 SPKL_MUTE 1 7 SPKVU 0 SPKLZC 6 0 5:0 SPKL_VOL [5:0] 11_1001 8 SPKR_MUTE 1 SPKVU SPKRZC 0 SPKR_VOL [5:0] 5:0 11_1001 Pre-Production DESCRIPTION Left Speaker Output Mute ...
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... Pre-Production ANALOGUE OUTPUTS The WM8903 has eight analogue output pins: • Headphone outputs, HPOUTL and HPOUTR • Line outputs, LINEOUTL and LINEOUTR • Differential line outputs, LON/LOP and RON/ROP The output signal paths and associated control registers are illustrated in Figure 33. ...
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... WM8903 EXTERNAL COMPONENTS FOR GROUND-REFERENCED OUTPUTS In the case of the ground referenced outputs HPOUTL, HPOUTR, LINEOUTL and LINEOUTR recommended to connect a zobel network to the audio output pins for best audio performance in all applications. The components of the zobel network have the effect of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions ...
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... Table 43. The analogue circuits in the WM8903 require a bias current. The normal bias current is enabled by setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also. The normal bias current can also be controlled using the ISEL field as described in Table 43 ...
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... VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the VMID reference voltage being applied. The WM8903 incorporates pop-suppression circuits which address these requirements. The alternate current source (Start-Up Bias) is enabled by STARTUP_BIAS_ENA. The start-up bias is selected (in place of the normal bias) by POBCTRL ...
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... Write Sequencer” section. In these cases, the user does not need to set these register fields directly. The analogue inputs to the WM8903 and the Differential Line (Speaker) outputs are biased to VMID in normal operation. In order to avoid audible pops caused by a disabled signal path dropping to AGND, the WM8903 can maintain these connections at VMID when the relevant input or output stage is disabled ...
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... WM8903 The register bits relating to pop suppression control are defined in Table 47. REGISTER ADDRESS R5 (05h) VMID Control 0 R65 (41h) R90 (5Ah) Analogue BIT LABEL DEFAULT 7 VMID_TIE_ENA 0 6 BUFIO_ENA 0 0 VMID_BUF_ENA 0 1 SPK_DISCHARG VROI 0 HPL_RMV_SHOR HPL_ENA_OUTP HPL_ENA_DLY 0 4 HPL_ENA ...
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... LINEOUTR_RMV 0 _SHORT 2 LINEOUTR_ENA 0 _OUTP 1 LINEOUTR_ENA 0 _DLY 0 LINEOUTR_ENA 0 WM8903 DESCRIPTION Removes LINEOUTL short 0 = LINEOUTL short enabled 1 = LINEOUTL short removed In normal operation, this bit is set to 1 Enables LINEOUTL output stage 0 = Disabled 1 = Enabled Enables LINEOUTL intermediate stage 0 = Disabled 1 = Enabled Enables LINEOUTL input stage 0 = Disabled ...
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... CHARGE PUMP CLOCK The charge pump clock is derived from MCLK, i.e. an MCLK signal must be present for the charge pump to function. The clock division from MCLK is handled transparently by the WM8903 without user intervention, as long as MCLK and sample rates are set correctly (see “Clocking and Sample Rates” ...
Page 73
... Table 48 Charge Pump Control DC SERVO The WM8903 provides a DC servo circuit on the headphone and line outputs in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs remains within 1.5mV of ground. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption ...
Page 74
... DC Servo is later enabled via the DCS_ENA bits. An alternative method to apply known correction settings is to read the correction values from the WM8903 register map and to store these for later use. After DC offset correction has been performed, the applicable correction values can be read from the fields in the Servo Readback registers R81 to R84 described in Table 50 ...
Page 75
... DCS_LOUTL_WRITE_VAL [7:0] DCS_LOUTR_WRITE_VAL 7:0 [7:0] 7:0 DCS_HPOUTL_INTEG [7:0] 7:0 DCS_HPOUTR_INTEG [7:0] 7:0 DCS_LOUTL_INTEG [7:0] 7:0 DCS_LOUTR_INTEG [7:0] WM8903 DEFAULT DESCRIPTION 0000_0000 Value to send to Left Headphone Output Servo in a WRITE mode Two’s complement format. LSB is 0.25mV. Range is +/-32mV Value to send to Right 0000_0000 Headphone Output Servo in a WRITE mode Two’s complement format. ...
Page 76
... Figure 37). Additionally, two “mixed” modes (BCLK as input, LRC as output and vice versa) can be selected. When BCLK is not selected (GP5_FN ≠ 1), the WM8903 uses the MCLK input as the Bit Clock, provided that BCLK_DIR is set configure BCLK as an input, ie. BCLK slave mode. This ...
Page 77
... All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. Time Division Multiplexing (TDM) is available in all four data format modes. The WM8903 can be programmed to send and receive data in one of two time slots. ...
Page 78
... WM8903 The register bits controlling audio data format and word length are summarised in Table 53. REGISTER ADDRESS R25 (19h) Audio Interface 1 Table 53 Audio Data Format Control In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition ...
Page 79
... In device slave mode, Figure 43 and Figure 44 possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse Justified Audio Interface (assuming n-bit word length) WM8903 st nd (mode (mode A) PP, Rev 3.1, August 2009 ...
Page 80
... WM8903 Figure 41 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) Figure 42 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) Figure 43 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) w Pre-Production PP, Rev 3.1, August 2009 80 ...
Page 81
... Pre-Production Figure 44 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=0, Slave) TIME DIVISION MULTIPLEXING (TDM) TDM allows more than two devices to share a single digital audio bus, as shown below. Figure 45 TDM with WM8903 as Master w BCLK LRC WM8903 Processor ADCDAT DACDAT BCLK Third LRC audio ...
Page 82
... When using such a scheme recommended to add pull-down resistors to the DACDAT and ADCDAT lines, as shown in Figure 45, and Figure 46. Note: The WM8903 is a 24-bit device. In 32-bit mode (AIF_WL=11), the 8 LSBs are ignored on the receiving side and not driven on the transmitting side. ...
Page 83
... When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as shown in Figure 47 to Figure 51. Figure 47 TDM in Right-Justified Mode Figure 48 TDM in Left-Justified Mode Figure 49 TDM Mode WM8903 PP, Rev 3.1, August 2009 83 ...
Page 84
... Figure 51 TDM in DSP Mode B COMPANDING The WM8903 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 55. Companding converts 13 bits (μ-law bits (A-law bits using non-linear quantization. This provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization ...
Page 85
... Figure 52 μ-Law Companding 120 100 Figure 53 A-Law Companding w F( μ|x μ) } for -1 ≤ x ≤ for x ≤ 1/A } for 1/A ≤ x ≤ 1 u-law Companding 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0 0 0.2 0.4 Normalised Input 0.5 0.6 0.7 0.8 0.9 1 0.6 0.8 1 PP, Rev 3.1, August 2009 WM8903 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 ...
Page 86
... WM8903 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for μ-law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as shown in Table 56 ...
Page 87
... Pre-Production CLOCKING AND SAMPLE RATES The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. When the DAC and ADC are both enabled, they operate at the same sample rate, f Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation, or ADC in USB mode ...
Page 88
... WM8903 CONTROL INTERFACE CLOCKING In certain configurations, such as analog bypass to differential line outputs, WM8903 can be used without MCLK (compared to LINEOUTL/R, which requires the charge pump hence requires MCLK). Without MCLK applied, CLK_SYS_ENA should be left in its default state otherwise there is limited access to the register map as detailed in Table 58. ...
Page 89
... Pre-Production CLOCKING REGISTERS The WM8903 clocking is configured using the register bits defined in Table 61. REGISTER ADDRESS R20 (14h) Clock Rates 0 R21 (15h) Clock Rates 1 R22 (16h) Clock Rates 2 Table 61 Clocking Control w BIT LABEL DEFAULT 0 MCLKDIV2 0 CLK_SYS_RAT 13:10 0011 E [3:0] 9:8 CLK_SYS_MOD 00 E [1:0] 3:0 SAMPLE_RATE 1000 [3:0] 2 CLK_SYS_ENA ...
Page 90
... MCLK itself is exact. DIGITAL MICROPHONE When GPIO1/DMIC_LR is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports Digital Microphone operation at a multiple of the ADC sampling rate. The precise clock frequency varies according to the MCLK frequency, the SAMPLE_RATE field and other settings. The clock frequency is always within the range 1MHz - 3MHz, and some examples are shown in Table 63 ...
Page 91
... Pre-Production GENERAL PURPOSE INPUT/OUTPUT (GPIO) The WM8903 provides five multi-function pins which can be configured to provide a number of different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins are: • GPIO1/DMIC_LR • GPIO2/DMIC_DAT • GPIO3/ADDR • INTERRUPT (GPIO4) • ...
Page 92
... BCLK is the default function of GPIO5. This may be input or output. Note that, when BCLK is enabled on this pin (GP5_FN = 1h), the other GPIO control fields for this pin have no effect. When BCLK is not enabled on this pin (GP5_FN ≠ 1h), the WM8903 uses the MCLK input as the Bit Clock. See “Digital Audio Interface” for further details. ...
Page 93
... GP3_IP_CFG 1 GP3_LVL 4 0 GP3_PD GP3_PU 0 1 GP3_INTMODE 0 WM8903 DESCRIPTION Output pin configuration 0 = CMOS 1 = Open-drain Input pin configuration 0 = Active low 1 = Active high GPIO Output Level (when GP2_FN = 00000 Logic Logic 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100kΩ) ...
Page 94
... WM8903 REGISTER ADDRESS R119 (77h) GPIO Control 4 R120 (78h) GPIO Control 5 w BIT LABEL DEFAULT 0 GP3_DB 0 13:8 GP4_FN[5:0] 00_0010 7 GP4_DIR 0 6 GP4_OP_CFG 0 GP4_IP_CFG 5 1 GP4_LVL GP4_PD 0 2 GP4_PU 0 1 GP4_INTMODE 0 0 GP4_DB 0 13:8 GP5_FN[5:0] 00_0001 7 GP5_DIR 1 6 GP5_OP_CFG 0 GP5_IP_CFG 5 1 Pre-Production DESCRIPTION ...
Page 95
... GP5_PD GP5_PU 0 1 GP5_INTMODE 0 0 GP5_DB 0 WM8903 DESCRIPTION GPIO Output Level (when GP5_FN = 00000 Logic Logic 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100kΩ) GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100kΩ) GPIO Interrupt Mode ...
Page 96
... INTERRUPT pin (GP4_FN = 2h), but the INTERRUPT pin can also be used to support other functions. See “General Purpose Input/Output (GPIO)” for details of how to configure GPIO pins for Interrupt (IRQ) output. The WM8903 Interrupt Controller circuit is illustrated in Figure 54. The associated control fields are described in Table 66. GPIO_IRQ[1] ...
Page 97
... IM_GP4_EINT 1 2 IM_GP3_EINT 1 1 IM_GP2_EINT 1 WM8903 DESCRIPTION MICBIAS Short Circuit detect IRQ status 0 = Short Circuit current IRQ not set 1 = Short Circuit current IRQ set MICBIAS Current detect IRQ status 0 = Current detect IRQ not set 1 = Current detect IRQ set Write Sequencer Busy IRQ status ...
Page 98
... In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM8903). The default device ID for the WM8903 is 0011010 (0x34h). Alternatively, the device ID can be set to 0011011 (0x36) by pulling the GPIO3/ADDR pin high during device start-up, when the internal power- on reset signal PORB (see “ ...
Page 99
... Pre-Production The WM8903 supports the following read and write operations: • • • • The data format for these operations is shown below Terminology used in the following figures: TERMINOLOGY Table 68 Control Interface Terminology Figure 56 Single Write Figure 57 Single Read Figure 58 Multiple Write using Auto-increment ...
Page 100
... WM8903 CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8903 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. Default sequences for Start-Up and Shut-Down are provided (see “ ...
Page 101
... WSEQ_START_ 00_0000 INDEX [5:0] 9:4 WSEQ_CURRE 00_0000 NT_INDEX [5:0] 0 WSEQ_BUSY 0 WM8903 DESCRIPTION Write Sequencer / Mic Detect Clock Enable Disabled 1 = Enabled Previously called WSEQ_ENA. Writing this bit aborts the current sequence and returns control of the device back to the serial control interface. Writing this bit starts the write ...
Page 102
... WM8903 WSEQ_DATA_START is a 4-bit field which identifies the LSB position within the selected Control Register to which the data should be written. Setting WSEQ_DATA_START = 0100 will cause 1-bit data to be written to bit 4. With this setting, 4-bit data would be written to bits 7:4 and so on. WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the need for read-modify-write procedures ...
Page 103
... WSEQ_EOS 0 WSEQ_DELA 11:8 0000 Y [3:0] 7:0 WSEQ_DATA 0000_0000 [7:0] WM8903 DESCRIPTION Sequence Write Index. This is the memory location to which any updates to R109 and R110 will be copied RAM addresses Width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits ...
Page 104
... Figure 60 Control Write Sequencer Example DEFAULT SEQUENCES When the WM8903 is powered up, two Control Write Sequences are available through ROM/default settings. The purpose of these sequences, and the register write required to initiate them is summarised in Table 71. In both cases a single register write will initiate the sequence ...
Page 105
... Bit 0 00h 0h 0b Bit 4 00h 0h 0b Bit 0 01h 6h 0b Bit 0 00h 0h 0b Bit 0 11h 0h 0b WM8903 DESCRIPTION POBCTRL = 1 ISEL = 10 STARTUP_BIAS_ENA = 1 BIAS_ENA = 0 SPK_DISCHARGE = 1 Wait 32ms SPKL_ENA = 1 SPKR_ENA = 1 SPK_DISCHARGE = 0 VMID_TIE_ENA = 1 BUFIO_ENA = 1 VMID_IO_ENA = 1 VMID_SOFT = 10 VMID_RES = 11 VMID_BUF_ENA = 1 Wait 128ms SPKL_ENA = 0 SPKR_ENA = 0 VMID_SOFT = 00 VMID_RES = 01 BIAS_ENA = 1 ...
Page 106
... WM8903 WSEQ REGISTER WIDTH INDEX ADDRESS 19 R94 (5Eh) 8 bits 20 R90 (5Ah) 8 bits 21 R94 (5Eh) 8 bits 22 R69 (45h) 2 bits 23 R67 (43h) 4 bits 24 R67 (43h) 4 bits 25 R255 (FFh) 1 bit 26 R90 (5Ah) 8 bits 27 R94 (5Eh) 8 bits w START DATA DELAY EOS Bit 0 11h 0h 0b Bit 0 ...
Page 107
... Bit 0 77h 0h 0b Bit 0 77h 0h 0b Bit 0 00h 0h 0b Bit 0 00h 0h 0b Bit 0 00h 0h 0b WM8903 DESCRIPTION HPL_RMV_SHORT = 1 HPL_ENA_OUTP = 1 HPL_ENA_DLY = 1 HPL_ENA = 1 HPR_RMV_SHORT = 1 HPR_ENA_OUTP = 1 HPR_ENA_DLY = 1 HPR_ENA = 1 LINEOUTL_RMV_SHORT = 1 LINEOUTL_ENA_OUTP = 1 LINEOUTL_ENA_DLY = 1 LINEOUTL_ENA = 1 LINEOUTR_RMV_SHORT = 1 LINEOUTR_ENA_OUTP = 1 LINEOUTR_ENA_DLY = 1 LINEOUTR_ENA = 1 End of Default Startup Sequence Spare step Spare step ...
Page 108
... WM8903 WSEQ REGISTER WIDTH INDEX ADDRESS 37 R98 (62h) 1 bit 38 R18 (12h) 2 bits 39 R22 (16h) 1 bit 40 R14 (0Eh) 2 bits 41 R15 (0Fh) 2 bits 42 R13 (0Dh) 2 bits 43 R4 (04h) 1 bit 44 R5 (05h) 2 bits 45 R5 (05h) 1 bit 46 R5 (05h) 1 bit 47 R5 (05h) 8 bits 48 R4 (04h) ...
Page 109
... POWER-ON RESET Figure 61 Internal Power on Reset Circuit Schematic The WM8903 includes an internal Power-On-Reset Circuit, as shown in Figure 61, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold. ...
Page 110
... WM8903 POWER-UP TIMING - DCVDD POWERED BEFORE AVDD Figure 63 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 63 shows the power-up sequence where DCVDD is powered up before AVDD assumed that DCVDD is at the specified operating voltage before AVDD rises to the minimum threshold this point, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset ...
Page 111
... Pre-Production QUICK START-UP AND SHUTDOWN The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number of register operations. The Control Write Sequencer is configured with default start-up settings that configure the device for DAC playback via Headphone and Line Output. Assuming a 12.288MHz external clock, the start-up sequence configures the device for 48kHz playback mode ...
Page 112
... WM8903 CHIP RESET AND DEVICE ID The WM8903 can be reset by writing to Register 0. This is a read-only register field, and the contents will not be affected by writing to this Register. The Device ID can be read back from Register 0. The Chip Revision ID can be read back from Register 1, as described in Table 76. ...
Page 113
... Pre-Production REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8903 can be configured using the Control Interface. REG NAME (0h) SW Reset and ID R1 (1h) Revision Number R4 (4h) Bias Control ...
Page 114
... WM8903 REG NAME (1Ah) Interface 2 R27 Audio (1Bh) Interface 3 R30 DAC Digital (1Eh) Volume Left R31 (1Fh) DAC Digital Volume Right R32 (20h) DAC Digital R33 (21h) DAC Digital DAC_M 1 R36 (24h) ADC Digital ...
Page 115
... ORT CP_EN CP_DY 0 0 WSEQ_WRITE_INDEX[4:0] WSEQ_ADDR[7:0] WSEQ_DATA[7:0] 0 WSEQ_START_INDEX[5:0] PP, Rev 3.1, August 2009 WM8903 0 DEFAULT _VOL 002Dh 002Dh 0039h 0039h 0139h 0139h VROI 0000h 0010h 00A4h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h NA LINEO ...
Page 116
... WM8903 REG NAME R112 Write (70h) Sequencer 4 R116 GPIO 0 0 (74h) Control 1 R117 GPIO 0 0 (75h) Control 2 R118 GPIO 0 0 (76h) Control 3 R119 GPIO 0 0 (77h) Control 4 R120 GPIO 0 0 (78h) Control 5 R121 Interrupt MICSH MICDE WSEQ (79h) Status 1 ...
Page 117
... Start-Up bias 10 Master Bias control 00 = Normal bias x 0 Normal bias x 0. Normal bias 11 = Normal bias x 1.5 0 Enables the Start-Up bias current generator 0 = Disabled 1 = Enabled 0 Enables the Normal bias current generator (for all analogue functions Disabled 1 = Enabled WM8903 DESCRIPTION PP, Rev 3.1, August 2009 117 ...
Page 118
... WM8903 REGISTER BIT LABEL ADDRESS R5 (05h) 7 VMID_TIE_ENA VMID Control 0 6 BUFIO_ENA 5 VMID_IO_ENA 4:3 VMID_SOFT[1:0] 2:1 VMID_RES[1:0] 0 VMID_BUF_ENA Register 05h VMID Control 0 REGISTER BIT LABEL ADDRESS R6 (06h) Mic 7:6 Reserved Bias Control 0 5:4 MICDET_THR [1:0] 3:2 MICSHORT_THR[1:0] 1 MICDET_ENA 0 MICBIAS_ENA Register 06h Mic Bias Control 0 w DEFAULT DESCRIPTION VMID buffer to Differential Lineouts ...
Page 119
... Note that the Low Power options is not supported when CLK_SYS_MODE=10 DEFAULT DESCRIPTION 0 Left Input PGA Enable 0 = disabled 1 = enabled 0 Right Input PGA Enable 0 = disabled 1 = enabled DEFAULT DESCRIPTION 0 Left Output Mixer Enable 0 = disabled 1 = enabled 0 Right Output Mixer Enable 0 = disabled 1 = enabled WM8903 PP, Rev 3.1, August 2009 119 ...
Page 120
... WM8903 REGISTER BIT LABEL ADDRESS R14 (0Eh) 1 HPL_PGA_ENA Power Management 2 0 HPR_PGA_ENA Register 0Eh Power Management 2 REGISTER BIT LABEL ADDRESS R15 (0Fh) 1 LINEOUTL_PGA_ENA Power Management 3 0 LINEOUTR_PGA_ENA Register 0Fh Power Management 3 REGISTER BIT LABEL ADDRESS R16 (10h) 1 MIXSPKL_ENA Power Management 4 0 MIXSPKR_ENA ...
Page 121
... Reserved if CLK_SYS_MODE = 01 (272*fs related clocks) 0000 = 68*fs 0001 = 136*fs 0010 = 204*fs 0011 = 272*fs 0100 = 408*fs 0101 = 544*fs 0110 = 816*fs 0111 = 1088 *fs 1000 = 1496*fs 1001 = 1632*fs WM8903 PP, Rev 3.1, August 2009 121 ...
Page 122
... WM8903 REGISTER BIT LABEL ADDRESS 9:8 CLK_SYS_MODE[1:0] 3:0 SAMPLE_RATE[3:0] Register 15h Clock Rates 1 REGISTER BIT LABEL ADDRESS R22 (16h) 2 CLK_SYS_ENA Clock Rates 2 1 CLK_DSP_ENA 0 TO_ENA Register 16h Clock Rates 2 w DEFAULT DESCRIPTION 1010 to 1111 = Reserved if CLK_SYS_MODE = 10 (250*fs related clocks) 0000 = 125*fs 0001 = 125*fs ...
Page 123
... Right DAC Data Source Select Right DAC outputs left channel data 1 = Right DAC outputs right channel data 0 ADC Companding Enable 0 = disabled 1 = enabled 0 ADC Companding Type 0 = μ-law 1 = A-law 0 DAC Companding Enable 0 = disabled 1 = enabled 0 DAC Companding Type 0 = μ-law 1 = A-law WM8903 PP, Rev 3.1, August 2009 123 ...
Page 124
... WM8903 REGISTER BIT LABEL ADDRESS R25 (19h) 13 AIFDAC_TDM Audio Interface 1 12 AIFDAC_TDM_CHAN 11 AIFADC_TDM 10 AIFADC_TDM_CHAN 9 LRCLK_DIR 7 AIF_BCLK_INV 6 BCLK_DIR 4 AIF_LRCLK_INV 3:2 AIF_WL[1:0] 1:0 AIF_FMT[1:0] Register 19h Audio Interface 1 w DEFAULT DESCRIPTION DAC TDM Enable Normal DACDAT operation 1 = TDM enabled on DACDAT 0 DACDAT TDM Channel Select ...
Page 125
... LRCLK duty cycle is only guaranteed with even values (8, 10, … … , 2047). DEFAULT DESCRIPTION 0 DAC Volume Update Writing this bit causes left and right DAC volume to be updated simultaneously 00h = Mute 01h = -71.625dB 02h = -71.250dB … (0.375dB steps) C0h to FFh = 0dB WM8903 PP, Rev 3.1, August 2009 125 ...
Page 126
... WM8903 REGISTER BIT LABEL ADDRESS R31 (1Fh) 8 DACVU DAC Digital Volume Right 7:0 DACR_VOL[7:0] 1100_0000 Right DAC Digital Volume Register 1Fh DAC Digital Volume Right REGISTER BIT LABEL ADDRESS R32 (20h) 11:8 ADCL_DAC_SVOL[3:0] DAC Digital 0 7:4 ADCR_DAC_SVOL[3:0] 3:2 ADC_TO_DACL[1:0] 1:0 ADC_TO_DACR[1:0] Register 20h DAC Digital 0 w DEFAULT ...
Page 127
... DESCRIPTION 0 ADC Volume Update Writing this bit causes left and right ADC volume to be updated simultaneously 00h = Mute 01h = -71.625dB 02h = -71.250dB … (0.375dB steps) C0h = 0dB … (0.375dB steps) EFh = +17.625dB F0h to FFh = +17.625dB WM8903 PP, Rev 3.1, August 2009 127 ...
Page 128
... WM8903 REGISTER BIT LABEL ADDRESS R37 (25h) 8 ADCVU ADC Digital Volume Right 7:0 ADCR_VOL[7:0] 1100_0000 Right ADC Digital Volume Register 25h ADC Digital Volume Right REGISTER BIT LABEL ADDRESS R38 (26h) 6:5 ADC_HPF_CUT[1:0] ADC Digital 0 4 ADC_HPF_ENA 1 ADCL_DATINV 0 ADCR_DATINV Register 26h ADC Digital 0 ...
Page 129
... Time delay can be calculated as 5/ fs, where fs is the sample rate. 1 Gain smoothing enable 0 = disabled 1 = enabled Quick release enable disabled 1 = enabled 1 Anti-clip enable 0 = disabled 1 = enabled 1 Gain smoothing hysteresis enable 0 = disabled 1 = enabled WM8903 PP, Rev 3.1, August 2009 129 ...
Page 130
... WM8903 REGISTER BIT LABEL ADDRESS R41 (29h) 15:12 DRC_ATTACK_RATE[3:0] DRC 1 11:8 DRC_DECAY_RATE[3:0] 7:6 DRC_THRESH_QR[1:0] 5:4 DRC_RATE_QR[1:0] 3:2 DRC_MINGAIN[1:0] 1:0 DRC_MAXGAIN[1:0] Register 29h DRC 1 w DEFAULT DESCRIPTION Gain attack rate (seconds/6dB) 0011 0000 = instantaneous 0001 = 363us 0010 = 726us 0011 = 1.45ms (default) 0100 = 2.9ms 0101 = 5.8ms 0110 = 11.6ms 0111 = 23.2ms 1000 = 46 ...
Page 131
... Compressor threshold T (dB) 000000 = 0dB 000001 = -0.75dB 000010 = -1.5dB … (-0.75dB steps) 111100 = -45dB 111101 = Reserved 11111X = Reserved 0_0000 Compressor amplitude at threshold YT (dB) 00000 = 0dB 00001 = -0.75dB 00010 = -1.5dB … (-0.75dB steps) 11110 = -22.5dB 11111 = Reserved WM8903 PP, Rev 3.1, August 2009 131 ...
Page 132
... WM8903 REGISTER BIT LABEL ADDRESS R44 (2Ch) 7 LINMUTE Analogue Left Input 0 4:0 LIN_VOL[4:0] Register 2Ch Analogue Left Input 0 w DEFAULT DESCRIPTION Left Input PGA Mute not muted 1 = muted 0_0101 Left Input PGA Volume If L_MODE = 00 (Single ended) OR L_MODE = 01 (Differential Line) 00000 -1.5 00001 -1 ...
Page 133
... If R_MODE = 1X (Differential MIC) 00000 Not valid 00001 +12 00010 +15 00011 +18 00100 +21 00101 (default) +24 00110 +27 00111 +30 01XXX +30 1XXXX +30 WM8903 PP, Rev 3.1, August 2009 133 ...
Page 134
... WM8903 REGISTER BIT LABEL ADDRESS R46 (2Eh) 6 INL_CM_ENA Analogue Left Input 1 5:4 L_IP_SEL_N[1:0] 3:2 L_IP_SEL_P[1:0] 1:0 L_MODE[1:0] Register 2Eh Analogue Left Input 1 REGISTER BIT LABEL ADDRESS R47 (2Fh) 6 INR_CM_ENA Analogue Right Input 1 5:4 R_IP_SEL_N[1:0] 3:2 R_IP_SEL_P[1:0] 1:0 R_MODE[1:0] Register 2Fh Analogue Right Input 1 w DEFAULT DESCRIPTION Left Input PGA Common Mode Rejection enable ...
Page 135
... DESCRIPTION Left DAC to Left Spkr Mixer Enable disabled 1 = enabled 0 Right DAC to Left Spkr Mixer Enable 0 = disabled 1 = enabled 0 Left Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled 0 Right Analogue Input to Left Spkr Mixer Enable 0 = disabled 1 = enabled WM8903 PP, Rev 3.1, August 2009 135 ...
Page 136
... WM8903 REGISTER BIT LABEL ADDRESS R53 (35h) 3 DACL_MIXSPKL_VOL Analogue Spk Mix Left 1 2 DACR_MIXSPKL_VOL 1 BYPASSL_MIXSPKL_VOL 0 BYPASSR_MIXSPKL_VOL Register 35h Analogue Spk Mix Left 1 REGISTER BIT LABEL ADDRESS R54 (36h) 3 DACL_TO_MIXSPKR Analogue Spk Mix Right 0 2 DACR_TO_MIXSPKR 1 BYPASSL_TO_MIXSPKR 0 BYPASSR_TO_MIXSPKR Register 36h Analogue Spk Mix Right 0 ...
Page 137
... Writing this bit will update HPOUTL and HPOUTR volumes simultaneously. 0 Right Headphone Output Zero Cross Enable 0 = disabled 1 = enabled 10_1101 Right Headphone Output Volume 000000 = -57dB 000001 = -56dB (… 1dB steps) 111001 = 0dB (… 1dB steps) 111110 = +5dB 111111 = +6dB WM8903 PP, Rev 3.1, August 2009 137 ...
Page 138
... WM8903 REGISTER BIT LABEL ADDRESS R59 (3Bh) 8 LINEOUTL_MUTE Analogue OUT2 Left 7 LINEOUTVU 6 LINEOUTLZC 5:0 LINEOUTL_VOL[5:0] Register 3Bh Analogue OUT2 Left REGISTER BIT LABEL ADDRESS R60 (3Ch) 8 LINEOUTR_MUTE Analogue OUT2 Right 7 LINEOUTVU 6 LINEOUTRZC 5:0 LINEOUTR_VOL[5:0] Register 3Ch Analogue OUT2 Right w DEFAULT DESCRIPTION Left Line Output Mute ...
Page 139
... Writing this bit will update LON/LOP and RON/ROP volumes simultaneously. 0 Right Speaker Output Zero Cross Enable 0 = disabled 1 = enabled 11_1001 Right Speaker Output Volume 000000 = -57dB 000001 = -56dB (… 1dB steps) 111001 = 0dB (… 1dB steps) 111110 = +5dB 111111 = +6dB WM8903 PP, Rev 3.1, August 2009 139 ...
Page 140
... WM8903 REGISTER BIT LABEL ADDRESS R65 (41h) 1 SPK_DISCHARGE Analogue SPK Output Control 0 0 VROI Register 41h Analogue SPK Output Control 0 REGISTER BIT LABEL ADDRESS R67 (43h) 4 DCS_MASTER_ENA DC Servo 0 3:0 DCS_ENA[3:0] Register 43h DC Servo 0 REGISTER BIT LABEL ADDRESS R69 (45h) 1:0 DCS_MODE[1:0] DC Servo 2 Register 45h DC Servo 2 ...
Page 141
... Two’s complement format. LSB is 0.25mV. Range is +/-32mV DEFAULT DESCRIPTION Output Servo. Two’s complement format. LSB is 0.25mV. Range is +/-32mV DEFAULT DESCRIPTION 0000_0000 Readback value on Left Line Output Servo. Two’s complement format. LSB is 0.25mV. Range is +/-32mV WM8903 PP, Rev 3.1, August 2009 141 ...
Page 142
... WM8903 REGISTER BIT LABEL ADDRESS R84 (54h) DCS_LOUTR_INTEG [7:0] 7:0 DC Servo Readback 4 Register 54h DC Servo Readback 4 REGISTER BIT LABEL ADDRESS R90 (5Ah) 7 HPL_RMV_SHORT Analogue HPL_ENA_OUTP 5 HPL_ENA_DLY 4 HPL_ENA 3 HPR_RMV_SHORT 2 HPR_ENA_OUTP 1 HPR_ENA_DLY 0 HPR_ENA Register 5Ah Analogue HP 0 REGISTER BIT LABEL ADDRESS R94 (5Eh) 7 LINEOUTL_RMV_SHORT ...
Page 143
... Bit position of the LSB of the data block 0000 written in this sequence step. 0000 = Bit 0 … 1111 = Bit 15 0000_0000 Control Register Address to be written to in this sequence step. WM8903 PP, Rev 3.1, August 2009 143 ...
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... WM8903 REGISTER BIT LABEL ADDRESS R110 (6Eh) 14 WSEQ_EOS Write Sequencer 2 11:8 WSEQ_DELAY[3:0] 7:0 WSEQ_DATA[7:0] Register 6Eh Write Sequencer 2 REGISTER BIT LABEL ADDRESS R111 (6Fh) 9 WSEQ_ABORT Write Sequencer 3 8 WSEQ_START 5:0 WSEQ_START_INDEX[5:0] Register 6Fh Write Sequencer 3 REGISTER BIT LABEL ADDRESS R112 (70h) 9:4 WSEQ_CURRENT_INDEX[5:0] Write Sequencer 4 ...
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... Logic 1 1 GPIO Pull-Down Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 100kΩ) 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100kΩ) 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced WM8903 PP, Rev 3.1, August 2009 145 ...
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... WM8903 REGISTER BIT LABEL ADDRESS R117 (75h) 13:8 GP2_FN[5:0] GPIO Control 2 7 GP2_DIR 6 GP2_OP_CFG 5 GP2_IP_CFG 4 GP2_LVL 3 GP2_PD 2 GP2_PU 1 GP2_INTMODE 0 GP2_DB Register 75h GPIO Control 2 w DEFAULT DESCRIPTION GPIO 2 Pin Function select 00_0000 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input ...
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... Logic 1 GPIO Pull-Down Enable Pull-down disabled 1 = Pull-down enabled (Approx 100kΩ) 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100kΩ) 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced WM8903 PP, Rev 3.1, August 2009 147 ...
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... WM8903 REGISTER BIT LABEL ADDRESS R119 (77h) 13:8 GP4_FN[5:0] GPIO Control 4 7 GP4_DIR 6 GP4_OP_CFG 5 GP4_IP_CFG 4 GP4_LVL 3 GP4_PD 2 GP4_PU 1 GP4_INTMODE 0 GP4_DB Register 77h GPIO Control 4 w DEFAULT DESCRIPTION GPIO 4 Pin Function select 00_0010 00h = GPIO output 01h = Reserved 02h = IRQ output 03h = GPIO input ...
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... Logic 1 GPIO Pull-Down Enable Pull-down disabled 1 = Pull-down enabled (Approx 100kΩ) 0 GPIO Pull-Up Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 100kΩ) 0 GPIO Interrupt Mode 0 = Level triggered 1 = Edge triggered 0 GPIO de-bounce 0 = GPIO is not debounced 1 = GPIO is debounced WM8903 PP, Rev 3.1, August 2009 149 ...
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... WM8903 REGISTER BIT LABEL ADDRESS R121 (79h) 15 MICSHRT_EINT Interrupt Status 1 14 MICDET_EINT 13 WSEQ_BUSY_EINT 4 GP5_EINT 3 GP4_EINT 2 GP3_EINT 1 GP2_EINT 0 GP1_EINT Register 79h Interrupt Status 1 w DEFAULT DESCRIPTION MICBIAS Short Circuit detect IRQ status Short Circuit current IRQ not set 1 = Short Circuit current IRQ set ...
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... MICBIAS Short Circuit detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold 0 MICBIAS Current Detect polarity 0 = Detect current increase above threshold 1 = Detect current decrease below threshold DEFAULT DESCRIPTION 0 Interrupt Output polarity 0 = Active high 1 = Active low WM8903 PP, Rev 3.1, August 2009 151 ...
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... WM8903 REGISTER BIT LABEL ADDRESS R164 (A4h) 9 ADC_DIG_MIC Clock Rate Test 4 Register A4h Clock Rate Test 4 REGISTER BIT LABEL ADDRESS R172 (ACh) 6:4 PGA_BIAS [2:0] Analogue Output Bias 0 Register ACh Analogue Output Bias 0 REGISTER BIT LABEL ADDRESS R187 (BBh) 2:0 OUTPUTS_BIA S [2:0] Analogue Output Bias ...
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... Capacitor positioning Decouplers and charge pump capacitors should be positioned as close to WM8903 as possible. C8, C9, C16 are the most important. C1, C2, C3, C4, C17, C18 should also be very close to WM8903. (3) Zobel Network All Zobel networks are a requirement if either HPOUT or LINEOUT is used. See datasheet text. ...
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... The sequence assumes that the polling of the control interface, by checking the interrupt flags, has been used to monitor changes in the microphone insertion or hook switch detection functions, rather than connection of a WM8903 GPIO. This means that the maximum possible mechanical bounce times for mic insertion and removal must be understood by the software programmer. ...
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... Pre-Production Figure 65 Mic Insert and Hook Switch Detect: Example MICBIAS Current Plot w WM8903 PP, Rev 3.1, August 2009 155 ...
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... GPIO is likely to simplify the rejection of mechanical bounce. Changes of state in the GPIO pin are also subject to the time delays t Further details can be found in the applications note WAN_0213 “WM8903 ECM mic detection using MICBIAS current”. w DETAILS , in which case the host processor should not set MICDET_INV = 1 until step 3 ...
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... E2 SEE DETAIL B aaa ccc aaa ccc C A 0.08 C bbb A1 DETAIL B MAX NOTE 0.60 0.05 0.25 1 3.65 2 3.65 2 0.45 DM051.A TOP VIEW D E DETAIL A PIN #1 1 IDENTIFICATION 40x b CHAMFER R0.300 X 45 EXPOSED GND PADDLE 1 PP, Rev 3.1, August 2009 WM8903 o 157 ...
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... WM8903 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...