wm9081 Wolfson Microelectronics plc, wm9081 Datasheet - Page 65

• Manufacturer Part Number: wm9081
• Description: Mono Dac With 2.6w Class Ab/d Speaker Driver, Dynamic Range Controller And Retune Mobile Parametric Equalizer
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
CLOCKING AND SAMPLE RATES
w
The internal clocks for the WM9081 are all derived from a common internal clock source, CLK_SYS.
This clock is the reference for the DSP / DAC core functions, digital audio interface, Class D
switching amplifier, write sequencer and other internal functions.
CLK_SYS can either be derived directly from MCLK, or may be generated from a Frequency Locked
Loop (FLL) using MCLK, BCLK or LRCLK as a reference. All commonly-used audio sample rates can
be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wider
range of MCLK frequencies. To avoid audible glitches, all clock configurations must be set up before
enabling playback. The FLL can be used to generate a free-running clock in the absence of an
external reference source; see “Frequency Locked Loop (FLL)” for further details.
The WM9081 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The core
clocking requirements of the WM9081 are automatically configured according to the selected Sample
Rate and the applicable CLK_SYS / fs ratio. These parameters are contained in the SAMPLE_RATE
and CLK_SYS_RATE register fields respectively.
A slow clock, TOCLK, is used to set the timeout period for volume updates when zero-cross detect is
used. This clock is enabled by CLK_TO_ENA and controlled by CLK_TO_DIV.
A clock output, OPCLK, can be derived from CLK_SYS and output on the MCLK pin to provide
clocking to other devices. This clock is enabled by CLK_OP_ENA and controlled by CLK_OP_DIV.
This feature is only available when MCLK is not selected as an input to the WM9081.
In master mode, BCLK is derived from CLK_SYS via a programmable divider set by BCLK_DIV. In
master mode, the LRCLK is derived from BCLK via a programmable divider LRCLK_RATE. The
LRCLK can be derived from an internal or external BCLK source, allowing mixed master/slave
operation. See “Digital Audio Interface Control” for details of the BCLK and LRCLK configuration.
The control registers associated with Clocking and Sample Rates are shown in Table 37 to Table 39.
The overall clocking scheme for the WM9081 is illustrated in Figure 53.
PP, Rev 3.0, April 2009
WM9081
65