wm9704q Wolfson Microelectronics plc, wm9704q Datasheet
wm9704q
Related parts for wm9704q
wm9704q Summary of contents
Page 1
... GPIO pins. WM9704Q is interchangeable with AC’97 Codecs from Wolfson and other suppliers in the basic Revision 2.1 mode. WM9704Q is fully operable with 3.3V or 5.0V or mixed 3.3/5.0V supplies and is packaged in an industry standard 48-pin TQFP package. BLOCK DIAGRAM ...
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... WM9704Q PIN CONFIGURATION DVDD1 1 XTLIN 2 XTLOUT 3 DVSS1 4 SDATAOUT 5 BITCLK 6 DVSS2 7 SDATAIN 8 DVDD2 9 SYNC 10 RESETB 11 PCBEEP ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits ...
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... AVDD -100mV +100mV AVSS Near rail to AVDD +100mV rail -100mV 2/5 AVDD AVDD/2 3/5 AVDD 75 Buffered CAP2 Buffered CAP2 Buffered CAP2 Buffered CAP2 -5 - Rev 2.3 January 2001 WM9704Q UNIT UNIT kohms ...
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... WM9704Q Test Characteristics: AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T PARAMETER DAC Circuit Specifications (AVDD = 5V) 48kHz sampling SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction ...
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... C to +70 C, unless otherwise stated A SYMBOL TEST CONDITIONS V = 1.65V REF -9dBV input 20 to 20kHz -3dBV input At any gain At max gain At 0db gain At max gain At 0db gain 20 to 20kHz WM9704Q MIN TYP MAX 82 0 19,200 19,200 28,800 28,800 - 0.7 0 ...
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... WM9704Q PIN DESCRIPTION PIN NAME DVDD1 1 2 XTLIN XTLOUT 3 4 DVSS1 SDATAOUT 5 6 BITCLK DVSS2 7 8 SDATAIN DVDD2 9 10 SYNC RESETB 11 12 PCBEEP 13 PHONE 14 AUXL 15 AUXR 16 VIDEOL 17 VIDEOR 18 CDL 19 CDGND 20 CDR 21 MIC1 22 MIC2 23 LINEINL 24 LINEINR 25 AVDD1 26 AVSS1 27 VREF(1) 28 VREFOUT 29 AFILT1(1) 30 MODE0 ...
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... C to +70 A SLOT 1 SLOT 2 SYNC WRITE DON’T DATA PR4 TO 0X20 CARE t S2_PDOWN SYMBOL t s2_PDOWN t RST_LOW SYMBOL t RST_LOW t RST2_CLK WM9704Q o C, unless otherwise stated o C, unless otherwise stated MIN TYP MAX 1.0 t RST2CLK MIN TYP MAX 1.0 162.8 PD Rev 2.3 January 2001 UNIT s UNIT s ns ...
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... WM9704Q WARM RESET BIT_CLK Figure 3 Warm Reset Timing SYNC active high pulse width SYNC inactive to BIT_CLK startup delay CLOCK SPECIFICATIONS BIT_CLK Figure 4 Clock Specifications (50pF External Load) PARAMETER BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BIT_CLK high pulse width (Note 1) BIT_CLK low pulse width (Note 1) ...
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... DOUT DOUT SYMBOL trise tfall trise tfall trise trise trise tfall MIN TYP MAX 15.0 5.0 HOLD MIN TYP MAX 2 CLK 2 CLK 2 SYNC 2 SYNC 2 DIN 2 DIN 2 DOUT 2 DOUT PD Rev 2.3 January 2001 WM9704Q UNIT ns ns UNIT ...
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... WM9704Q SYSTEM INFORMATION RESET BITCLK AC’97 SYNC DIGITAL SDATAIN CONTROLLER SDATAOUT { CID0 CHIP SELECT CID1 Figure 7 WM9704Q in Typical Quad Mode Application WOLFSON MICROELECTRONICS LTD CD, VIDEO, AUX, MIC1 LINEINL/R PC_BEEP PHONE MIC2 WM9704Q 10 41 (QUAD MODE ...
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... In this case, the WM9704Q will process the 16-bit word along with 0 padding bits in the 2 LSB locations (to make 18- bit). At the ADC output, WM9704Q will provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’ ...
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... WM9704Q QUAD MODE In this mode the additional 2 DAC channels are enabled, using the line level output pins 39 and 41 as outputs. An additional mixer block in this path allows the analogue mix, excluding the front DAC channels summed into the rear channel mix. Additional gain controls (PGAs) are provided to allow adjustment of front and rear mix levels separately (registers 72h and 74h) prior to summing the analogue mix to these channels ...
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... Connect BITCLK from the AC’97 to BCLK on the DAC. Connect pin 43 from the WM9704Q to the LRCLK on the DAC. Connect one of the two data pins WM9704Q to the SDATA pin on the DAC. Note that the DAC must support serial interface data rates 12.5MHz (Wolfson DACs such as the WM8725 and WM8733 support this) ...
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... WM9704Q The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to register 22h bits Value 0h is disable, value Fh is maximum effect. Typically a value optimum. The user interface would most typically use a slider type of control to allow the user to adjust the level of enhancement to suit the program material ...
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... Volume Table 5 Gain Control Register Location Versus Mode and ID MASTER/SLAVE ID0/1 SUPPORT WM9704Q supports operation as either a master or a slave codec. Configuration of the device as either a master slave, is selected by tying the ID pins CID0 and CID1, pins 45 and 46 on the package. Fundamentally, a device identified as a master (ID = 00) produces BITCLK as an output, whereas a slave (any other ID) must be provided with BITCLK as an input ...
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... WM9704Q PIN 46 CID1 Ground Ground Table 6 ID Selection WM9704Q supports the AMAP function whereby selection will automatically map the data from the interface onto the PCM DACs. CODEC The Codec ID is available to the controller via registers 28h and C3, bits D15 and D14 ...
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... New definitions for Slave Codec Register Access Table 9 Slave Codec Register Access Slot 0-Bit Definitions CONTROL INTERFACE A digital interface has been provided to control the WM9704Q and transfer data to and from it. This serial interface is compatible with the Intel AC’97 specification as illustrated in Figure 7. The main control interface functions are: Control of analogue gain and signal paths through the mixer. Bi-directional transfer of ADC and DAC words to and from AC’ ...
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... SYNC is low is defined as the Data Phase. Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that the WM9704Q be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. ...
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... Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the Valid Frame bit this indicates that the current audio frame contains at least one time slot of valid data. The next 12-bit positions sampled by the WM9704Q indicate which of the corresponding 12 time slots contain valid data. ...
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... WM9704Q As an example, consider an 8-bit sample stream that is being played out to one of the WM9704Q’s DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the resolution of the implemented DAC (16 20-bit biasing will be introduced by the least significant bits. When mono audio sample streams are output from the AC’ ...
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... Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the WM9704Q is in the Codec Ready state or not. If the Codec Ready bit this indicates that the WM9704Q is not ready for normal operation. This condition is normal following the desertion of power on reset for example, while the WM9704Q’ ...
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... AC’97. SLOT 2: STATUS DATA PORT The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3:0) If slot 2 is tagged invalid by the WM9704Q, then the entire slot will be stuffed with 0s by the WM9704Q. WOLFSON MICROELECTRONICS LTD WM9704Q SAMPLES SYNC ASSERTION HERE SYNC AC’ ...
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... The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the WM9704Q to this low power, halted mode. Once the WM9704Q has been instructed to halt BIT_CLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal audio output and input frames can not be communicated in the absence of BIT_CLK ...
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... BIT_CLK. Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the WM9704Q. The WM9704Q will not respond with the activation of BIT_CLK until SYNC has been sampled low again by the WM9704Q ...
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... Production Data Support for the MSB of the volume level is not provided by the WM9704Q. If the MSB is written to, then the WM9704Q detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9704Q interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it ...
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... Table 16 General Purpose Register Function 3D CONTROL REGISTER (INDEX 22h) This register is used to control the centre and/or depth of the 3D stereo enhancement function built into of the AC ‘97 component. Only the depth bits DP0 to 3 have effect in the WM9704Q. DP3…DP0 WOLFSON MICROELECTRONICS LTD ...
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... When the AC-link Codec Ready indicator bit (SDATA_IN slot 0, bit 15 indicates that the AC- link and the WM9704Q control and status registers are in a fully operational state. The AC’97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready ...
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... Figure 13 illustrates one example of a procedure complete powerdown of the WM9704Q. From normal operation sequential writes to the Powerdown Register are performed to powerdown the WM9704Q a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9704Q’s digital interface (AC-link). ...
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... PCM converters. Default is the 48ks/s rate. Note that only Revision 2.1 recommended rates are supported by the WM9704Q, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. ...
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... These read/write registers control the output volume of the optional four PCM channels. Note that as WM9704Q only supports 4 internal DACs, depending upon which ID has been selected via the CID pins 45 and 46, these registers may or may not have effect. The fields behave the same as the master volume control register, which offers attenuation but no gain ...
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... Play Vendor ID code. The first character of that F0, the second character S7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In WM9704Q the vendor ID is set to WML3 if MODE1 = 0, and WML4 if MODE1 = 1. ...
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... WM9704Q SERIAL INTERFACE REGISTER MAP The following table shows the function and address of the various control bits that are loaded through the serial interface during write operations. Reg Name D15 D14 00h Reset X SE4 02h Master volume Mute X 04h Headphone vol. ...
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... AVSS NOTES: 1. Pins 27, 29 and 31 are internally connected recommended that AC-LINK capacitors only be connected to one of these pins C28 should be as close to WM9704Q as possible. 3. AGND and DGND should be connected as close to WM9704Q as possible. Figure 15 External Components Diagram WOLFSON MICROELECTRONICS LTD DVDD 1 ...
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... WM9704Q RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT SUGGESTED REFERENCE VALUE 10nF C5 to C17 470nF C18 1 F C19 0.1 F C20 10 F C21 0.1 F C22 10 F C23 0.1 F C24 10 F C25 0.1 F C26 10 F C27 100nF C28 47nF C29 to C33 10 F C34 and C35 22pF XT 24.576 MHz Table 25 External Component Values RECOMMENDATIONS FOR 3 ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD -C- ccc C SEATING PLANE MAX ----- 1.60 ----- 0.15 1.45 0.27 ----- 0.20 0. DM003 Rev 2.3 January 2001 WM9704Q 35 ...