isppac-powr1208p1 Lattice Semiconductor Corp., isppac-powr1208p1 Datasheet - Page 31

• Manufacturer Part Number: isppac-powr1208p1
• Description: In-system Programmable Power Supply Sequencing Controller And Precision Monitor
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispPAC-POWR1208P1 Data Sheet
FET Drivers: Allows the user to define ramp rates by controlling the current driven to the gate of the external FETs.
Maximum voltage levels and pin names are also set using this functional block. The four FET driver outputs
HVOUT1-4 can also be configured as open-drain digital logic outputs.
Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital out-
puts are open-drain and require a pull-up resistor.
Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the
four internal programmable timers used for sequence delay.
2
User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E
CMOS.
Figure 3-19. PAC-Designer LogiBuilder Screen
Programming of the ispPAC-POWR1208P1 is accomplished using the Lattice ispDOWNLOAD Cable. This cable
connects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the
JTAG TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry
that the user has defined during the design process.
Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been com-
pleted, the power supply to the ispPAC-POWR1208P1 can be set from 2.7V to 5.5V. Once programmed, the on-
2
chip non-volatile E
CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip
2
points for comparators etc. Upon powering the device up, the non-volatile E
CMOS bits control the device configu-
ration. If design changes need to be made such as adjusting comparator trip points or changes to the digital logic
functions, the device is simply re-programmed using the ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulation of the control sequence is provided using the software tools Waveform Editor and
Waveform Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simula-
tion engine combines the design file with a stimulus file (edited by the user with Waveform Editor) to produce an
output file that can be observed with the Waveform Viewer (Figure 3-20).
3-31