isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 21

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

DAC Address Mode Details
DAC Parallel Mode Addressing . The parallel address-
ing mode uses the eight external (D0-D7) data pins of the
ispPAC20 to address the DAC. The DMode (DAC
E
input data path is routed from E
directly from the parallel input data pins (DMode =1). In
addition, both serial input modes (JTAG/Direct and SPI)
must be disabled to access the parallel input mode. This
means the shift register option in the DAC port configu-
ration pop-up is selected, the ENSPI (Enable SPI serial
mode) logic input pin is low and the DMode logic input pin
is high. Data is latched into the parallel data latches on a
positive going edge of CS (Chip Select) and the output of
the DAC changes to its new value at this time according
to the setup timing constraints in the AC specification
waveform tables. When a device is first turned on, the
parallel data latches are initialized to code 80h, which
corresponds to 2.5V on both DAC analog output pins. To
otherwise start up with the value DAC code programmed
in E
logic input pin must remain low until the first data update
of the parallel input data latch at which time the contents
of the DAC reflect the parallel data input pins.
JTAG/E
mode is the only addressing mode where the ispPAC20
powers up with the DAC set to the input code stored in its
internal E
DAC defaults to input code 80h (2.5V on both output pins)
at turn on. The DAC can be changed while in this mode,
but only by a process of reprogramming the DAC E
memory cells themselves via routine JTAG commands.
This is sometimes desirable when a particular DAC
output operating point is reached that the system is then
required to “remember”. This update can be accom-
plished via programming the DAC directly through the
JTAG interface of the ispPAC20 without perturbing any of
the rest of the chip’s function or operation.
It should be noted, however, that the DAC outputs are
directly determined by the state of their E
memory. That means if the DAC E
grammed to change codes, the DAC output will follow the
E
reached. A DAC E
erase during which the output goes to minus full-scale
(-FS), then a write during which the output briefly goes to
plus full-scale (+FS) before the E
final programmed values and the output settles there as
well. This phenomenon only applies when in the JTAG/
E
Theory of Operation (Continued)
2
2
2
/parallel Mode) logic input pin determines whether the
transition states until their final programmed value is
serial address mode. In all other addressing modes,
2
memory (instead of the default 80h), the DMode
2
2
Serial Mode Addressing . The JTAG/E
configuration memory. In all other modes the
2
programming cycle consists of an
2
memory (DMode =0) or
2
cells transition to their
2
cells are repro-
2
configuration
2
serial
2
21
the DAC changes to its new value immediately after a
latch register is clocked.
JTAG/Direct Serial Mode Addressing . Unlike the pre-
vious method of addressing the ispPAC20 DAC from the
E
DAC via the serial input data latches. After a data word is
shifted into the serial input shift register via JTAG com-
mand (AddDAC), the DAC is immediately updated on the
falling edge of clock TCK in the UpdateDR state. The E
cells are bypassed entirely in this mode. The advantages
are that the DAC can be addressed separately from the
rest of the ispPAC20 via the serial JTAG interface and
can be continuously updated an unlimited number of
times. The serial data rate of 5MHz is much faster than
the settling time of the DAC making this an acceptable
way of addressing and changing the output for full speed
AC applications. It is, of course, also suitable for applica-
tions where the DAC output needs to be varied from time
to time, and the need to store the last code before power
down on-chip is not critical.
SPI Serial Mode Addressing . Finally, the ispPAC20 can
be addressed using a serial interface mode that is com-
patible with the industry standard SPI protocol (serial
peripheral interface, a Motorola trademark). Like the
JTAG/Direct serial mode, the DAC E
bypassed in SPI serial mode allowing the DAC to be
updated continuously and for an unlimited number of
cycles if desired. Whenever the ENSPI (enable SPI) pin
is high, the ispPAC20 is in the SPI serial addressing
mode and the 8 bits of DAC input data can be clocked in
with D0 (the LSB) being first in the data stream and D7
(the MSB) being last, if the device is selected by the CS
(chip select) pin being low. The data is latched in and the
DAC output changes on a subsequent rising edge of CS.
Comparator PACell Operation
The ispPAC20 has two programmable, double difference
comparator PACells on chip that include many user
programmable options to optimize their utility. These
comparators operate no differently than any standard
comparator, that is whenever the +(plus) input is positive
with respect to the -(minus) input, its logic output will be
high, otherwise they will be low. Unlike most other avail-
able comparators, however, inputs to the ispPAC20
comparator PACells are fully differential (true double-
difference comparators). Both the plus and minus inputs
of the ispPAC20 comparators have a Vin+ and a Vin- with
the differential input voltage defined as [(Vin+) - (Vin-)].
This means the comparator output is high whenever the
2
cells directly, JTAG/Direct serial mode interfaces the
Specifications ispPAC20
2
configuration is
2