isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 22

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

differential voltage on the +(plus) input is positive with
respect to the differential input voltage on the -(minus)
input.
Comparator Input Options
All inputs to the comparators can be accessed from
several different points including signals external to the
ispPAC20. When first shown in the PAC-Designer soft-
ware design entry screen, the inputs to the comparators
appear not to be connected to any signal source. In fact,
whenever no connection is indicated, the Vin+ and Vin-
lines (denoted by a single line in PAC-Designer) are both
connected to 2.5V DC. That means that if the minus input
were left unconnected in PAC-Designer, the differential
voltage on that input would be 0V (2.5V - 2.5V = 0V). At
this point any positive differential voltage on the plus
input of that comparator would result in a logic 1 output,
and any negative a logic 0.
The output of PACblock 2 (OA2) is available to any input
of CP1 or CP2 as is the external input pin, IN3. In the case
of a signal on IN3, it could be routed to one of the
PACblocks as well as the comparators to control a
switching threshold or other level determined event.
Using IN3 as a standalone input going only to one of the
comparators and the CPIN pin (comparator external
input), both the plus and minus inputs to the comparators
could come from entirely external signals.
The most common source for deriving reference levels
on the comparators would be directly from the internal
8-bit DAC. In addition to the 256 voltage levels being
directly available from the DAC, a constant 1.5V and 3.0V
is also available for setting a comparator input threshold.
These fixed values free the DAC to be used for other
circuit purposes such as nulling system offset voltages or
programming ADC reference inputs.
It should be noted that the plus input path of CP2
effectively performs a negation of the differential voltage
to that input (denoted by an additional inversion symbol
in PAC-Designer). The utility of this operation is that an
identical differential signal can be applied to the plus
inputs of both comparator PACells and result in a sym-
metrical window about 2.5V. For example if the +1.5VDC
input line is connected to both comparator plus inputs,
CP1’s plus input is +1.5V differential, and CP2’s plus
input is then -1.5V differential. If both minus inputs were
both connected to CPin in PAC-Designer (the external
comparator input pin), the result would be a logic 1 on
CP1 when the external input was below +1.5Vdiff and a
logic 1 on CP2 whenever it was above -1.5Vdiff. Further-
Theory of Operation (Continued)
22
more, the WINDOW (window compare output pin) which
is the exclusive OR of the two CPout pins would result in
a logic 0 any time the signal was between +-1.5Vdiff on
the external input and a logic 1 anytime it was outside that
window.
Optional Comparator Hysteresis
Another programming option provided for the user is the
ability to enable or disable comparator hysteresis. Hys-
teresis is useful in situations where a slow moving signal,
or an uncertain transition condition exists that would
otherwise result in excessive noise on the comparator
output. The magnitude of this hysteresis is nominally
47mV and can be either enabled or disabled in E
configuration memory and concurrently affects both com-
parators. It is symmetrical with respect to any input
change, which means that regardless of which direction
the input causing the state change comes from (with
respect to the reference input), it will have to change at
least 47mV above or below the reference to cause
another output state change. The default initial condition
of the hysteresis setting is on. Comparator hysteresis can
be disabled by selecting the appropriate edit symbol
command in PAC-Designer and making the change.
Polarity Control of IA4
Normally the gain and polarity for an individual IA (instru-
ment amplifier input) PACell is chosen from the range of
choices from -10 to +10 (in integer steps) directly in PAC-
Designer from a single gain setting listbox choice. With
the ispPAC20 this is the case for IA1, IA2 and IA3. IA4 on
the other hand, only has gain choices from -10 to -1
available in this particular dialog box. The reason is the
positive gains are actually realized by internally reversing
the polarity of the differential inputs, effectively multiply-
ing the ten negative gains by -1 to achieve the positive
gain values. With IA4, the control of this inversion
“routing” switch has been made externally available for
some unique device operating modes. The control is
made through the external PC (polarity control) pin, or
signals routed internally to this same input pin. See Table
4 and Figure 13 for complete PC pin operation details.
These comparator logic control/option modes are all
configured within PAC-Designer to achieve the operation
summarized in Table 4 and Figure 13. More information
is available in the online help file for PAC-Designer and
in application notes that describe the circuits made
possible by this on-chip logic.
Specifications ispPAC20
2