wm8804geds-v Wolfson Microelectronics plc, wm8804geds-v Datasheet
wm8804geds-v
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wm8804geds-v Summary of contents
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... SSOP package. S, left justified, right APPLICATIONS • AV processors and Hi-Fi systems • Music industry applications • DVD-P/DVD-RW • Digital TV http://www.wolfsonmicro.com/enews/ WM8804 Left, Right Justified or DSP 16/20/24 bit word lengths TM and DTS Production Data, March 2009, Rev 4.5 Copyright ©2009 Wolfson Microelectronics plc TM . ...
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WM8804 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ......................................................................... 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ...
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... Production Data PIN CONFIGURATION ( Top View ) ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8804GEDS/V -40 to +85 WM8804GEDS/RV -40 to +85 Note: Reel quantity = 2,000 w PACKAGE SENSITIVITY LEVEL 20-lead SSOP o C (Pb-free) 20-lead SSOP o C (Pb-free, tape and reel) MOISTURE PEAK SOLDERING TEMPERATURE o 260 C MSL3 o 260 C MSL3 PD, Rev 4 ...
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WM8804 PIN DESCRIPTION PIN NAME 1 SCLK 2 GPO0 / SWIFMODE 3 SDIN / HWMODE 4 SDOUT / GPO2 5 CSB / GPO1 6 RESETB 7 PVDD 8 PGND 9 CLKOUT 10 XOP 11 XIN 12 DOUT 13 DIN 14 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8804 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Ground PLL supply range Ground Notes: 1. PLL and digital supplies must always be within 0.3V of each other. 2. PLL and digital grounds must always be within 0.3V of each other. ...
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Production Data MASTER CLOCK TIMING MCLK Figure 1 Slave Mode MCLK Timing Requirements Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER System Clock Timing Information – Slave Mode MCLK System clock cycle ...
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WM8804 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK LRCLK DIN DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER SYMBOL Audio Data Input ...
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Production Data CONTROL INTERFACE – 3-WIRE MODE t CSS CSB t CSU SCLK SDIN SDO Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T ...
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WM8804 CONTROL INTERFACE – 2-WIRE MODE t STHO SDIN SCLK t SCY Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T PARAMETER Program Register ...
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Production Data DEVICE DESCRIPTION INTRODUCTION FEATURES • • • • • • • • • • The WM8804 is an IEC-60958 compatible S/PDIF transceiver with support for one received S/PDIF data stream and one transmitted S/PDIF data stream. The receiver ...
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WM8804 Frame 0 Sync preamble Figure 6 S/PDIF Format POWER UP CONFIGURATION The operating mode of the WM8804 is dependent upon the state of SDIN, SCLK, SDOUT, CSB and GPO0 when the device is powered hardware reset ...
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Production Data When the device powers up, all power up configuration pins are configured as inputs for a minimum of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based on 27MHz and ...
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WM8804 CONTROL INTERFACE OPERATION Control of the WM8804 is implemented in either hardware control mode or software control mode. The method of control is determined by sampling the state of the SDIN/HWMODE pin at power hardware ...
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Production Data 3-WIRE SERIAL CONTROL MODE REGISTER READ-BACK Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers can be read. These status registers are labelled as “read only” in the ...
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WM8804 Figure 10 3-Wire Control Interface Read-Back Method 2 2-WIRE SERIAL CONTROL MODE - REGISTER WRITE The WM8804 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus and each device has a ...
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Production Data Multiple consecutive register writes can be performed in 2-wire control mode by setting the CONT bit high. This method allows the entire register map to be defined in a one continuous write operation. Figure 12 2-Wire Serial Control ...
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WM8804 SOFTWARE REGISTER RESET Writing to register 0000000 will reset the WM8804. This will reset all register bits to their default values. The WM8804 is powered down by default so writing to this register will power down the device. DEVICE ...
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Production Data DIGITAL ROUTING CONTROL See page 20 for a full description of the signal routing options available in the WM8804. In Software control mode the value set in register TXSRC determines the S/PDIF transmitter data source. In hardware control ...
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WM8804 DIGITAL ROUTING CONTROL Figure 15 Digital Routing Paths within the WM8804 Digital signal routing within the WM8804 is controlled by the TXSRC register. In order to ensure proper operation when changing TXSRC, the S/PDIF transmitter module should be powered ...
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Production Data MASTER CLOCK AND PHASE LOCKED LOOP SOFTWARE MODE INTERNAL CLOCKING The WM8804 is equipped with a comprehensive clocking scheme that provides maximum flexibility and many configurable routing possibilities for the user in software mode. An overview of the ...
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WM8804 The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and appropriate external loading capacitors. The oscillator circuit contains a bias generator within the WM8804 and hence an external bias resistor is not required. ...
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Production Data REGISTER ADDRESS R3 PLL1 03h R4 PLL2 04h R5 PLL3 05h R6 PLL4 06h Table 21 User Mode PLL_K and PLL_N Multiplier Control PLL CONFIGURATION The PLL performs a configurable frequency multiplication of the input clock signal (f ...
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WM8804 REGISTER ADDRESS R6 PLL4 06h R7 PLL5 07h Table 22 Pre and Post PLL Clock Divider Control PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required MCLK frequency ...
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Production Data OSC PRE SCALE CLK (MHz) (MHz) (MHz 98.304 98.304 98.304 98.304 98.304 90.3168 90.3168 ...
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WM8804 REGISTER ADDRESS R28 AIFRX 1Ch Table 25 Audio Interface Mode Select When MCLK is configured as an output, the MCLK source and rate can be selected using the control bits shown in Table 26. The MCLK rate select can ...
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Production Data REGISTER ADDRESS R7 PLL5 07h R8 PLL6 08h Table 29 Clock Output (CLKOUT) Control S/PDIF TRANSMITTER When the S/PDIF transmitter is enabled and configured (using TXSRC) to use the S/PDIF received data, the S/PDIF transmitter is clocked from ...
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WM8804 The specified f reception of specific S/PDIF sample rates are as follows: • • The FREQMODE[1:0] bits are automatically controlled by the S/PDIF receiver when the receiver is enabled and do not need to be configured in any particular ...
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Production Data TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR FROM MODE 1 (176.4/192KHZ): Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz (mode 1)) will be flagged to the ...
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WM8804 HARDWARE MODE INTERNAL CLOCKING In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. An overview of the hardware mode clocking scheme ...
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Production Data S/PDIF TRANSMITTER The S/PDIF transmitter generates the S/PDIF frames, and outputs on the TX0 pin. The transmitted data can be sourced from one of two places, selectable using the TXSRC register. The transmitter can be powered down using ...
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WM8804 CHANNEL STATUS The Channel Status bits form a 192-frame block transmitted one bit per sub-frame. Each sub-frame forms its own 192-frame block. The WM8804 is a consumer mode device and only the first 40 bits of the block are ...
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Production Data REGISTER BIT LABEL ADDRESS R20 3:0 SRCNUM SPDTX3 14h 5:4 CHNUM1[1:0] 7:6 CHNUM2[1:0] Table 36 S/PDIF Transmitter Channel Status Bit Control Register 3 REGISTER BIT LABEL ADDRESS R21 3:0 FREQ[3:0] SPDTX4 15h 5:4 CLKACU[1:0] Table 37 S/PDIF Transmitter ...
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WM8804 REGISTER BIT ADDRESS R22 0 SPDTX5 16h 3:1 7:4 ORGSAMP Table 38 S/PDIF Transmitter Channel Status Bit Control Register 5 S/PDIF RECEIVER The S/PDIF receiver has one input. This input can be configured as either single ended CMOS or ...
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Production Data AUDIO DATA HANDLING The S/PDIF receiver recovers the data and VUCP bits from each sub-frame. The WM8804 can detect when the data is not in PCM format. See Non-Audio Detection section for more detail. The received data can ...
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WM8804 REGISTER BIT ADDRESS R13 0 RXCHAN1 0Dh (read-only 5:4 7:6 CHSTMODE Table 40 S/PDIF Receiver Channel Status Register 1 REGISTER BIT ADDRESS R14 7:0 CATCODE RXCHAN2 0Eh (read-only) Table 41 S/PDIF Receiver Channel Status Register 2 ...
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Production Data REGISTER BIT ADDRESS R16 3:0 RXCHAN4 10h 5:4 CLKACU[1:0] (read-only) Table 43 S/PDIF Receiver Channel Status Register 4 REGISTER BIT ADDRESS R17 0 RXCHAN5 11h (read-only) 3:1 RXWL[2:0] 7:4 ORGSAMP Table 44 S/PDIF Receiver Channel Status Register 5 ...
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WM8804 S/PDIF RECEIVER STATUS FLAGS There are several S/PDIF receiver status flags which are recorded by the WM8804. The flags are described in Table 45. These flags are available via GPIO pins or status registers. FLAG UNLOCK Unlock Flag Indicates ...
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Production Data NON_AUDIO Non-Audio Flag Logical OR of PCM_N and AUDIO_N CSUD Channel Status Update Indicates that channel status registers have updated and may be read back over the serial interface. DEEMPH De-emphasis Flag 0 = Recovered data has no ...
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WM8804 INTERRUPT GENERATION The INT_N flag indicates that a change of status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, CSUD, NON_AUDIO, CPY_N, REC_FREQ or DEEMPH status flags. To identify which flag caused the interrupt, the Interrupt ...
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Production Data Where the INT_N has been asserted by an update signal (UPD_NON_AUDIO, UPD_CPY_N, UPD_REC_FREQ, UPD_UNLOCK or UPD_DEEMPH) the S/PDIF Status Register (SPDSTAT) can be interrogated to establish the updated value of the flag. REGISTER BIT ADDRESS R12 0 SPDSTAT ...
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WM8804 ERROR HANDLING IN SOFTWARE MODE When the TRANS_ERR flag is asserted, it indicates that the recovered Rx S/PDIF sub-frame is corrupted. This corruption can due to a BI-Phase error, a parity error or a pre-amble error. When the INVALID ...
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Production Data NON-AUDIO DETECTION The SPDIF payload can contain PCM data for audio or non-audio applications. In the case where the payload contains the 96 bit synchronization code defined in IEC61937 then this indicates that the payload contains data which ...
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WM8804 DIGITAL AUDIO INTERFACE Audio data is transferred to and from the WM8804 via the digital audio interface. Data from the digital audio interface transmitter may be passed to the S/PDIF transmitter or data from the S/PDIF receiver may be ...
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Production Data Master/slave mode is selected with the following register: REGISTER ADDRESS R28 AIFRX 1Ch Table 55 Master/Slave Mode Select Register When operating in master mode, then the BCLK and LRCLK are derived from the sample rate of the S/PDIF ...
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WM8804 LRCLK BCLK DIN / DOUT Figure 18 Left Justified Mode RIGHT JUSTIFIED MODE In Right Justified Mode, the LSB of DIN is sampled by the WM8804 on the rising edge of BCLK preceding an LRCLK transition. The LSB of ...
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Production Data DSP MODE A In DSP Mode A, the MSB of the left channel data is sampled by the WM8804 on the second rising edge of BCLK following an LRCLK rising edge. The right channel data follows the left ...
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WM8804 ‘WITH FLAGS’ MODE The following diagrams illustrate the position of the status flags within the audio sample for each audio data format when ‘With Flags’ Mode is enabled. ‘With Flags’ Mode is only available on pin DOUT. The WM8804 ...
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Production Data Figure 26 DSP Mode A ‘With Flags’ Figure 27 DSP Mode B ‘With Flags’ w WM8804 PD, Rev 4.5, March 2009 49 ...
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WM8804 AUDIO INTERFACE CONTROL The register bits controlling the audio interface are summarised below. Note that dynamically changing the audio data format may cause erroneous operation, and hence is not recommended. REGISTER BIT ADDRESS R29 SPDIFRX1 1Dh R27 1:0 AIFTX ...
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Production Data Note 1: S/PDIF data frames contain a maximum of 24-bits of audio data. Note bit I for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles (48 BCLK cycles). ...
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WM8804 REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8804 can be configured using the Control Interface. Any unused bits which are not specified ...
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Production Data REGISTER BIT ADDRESS R00 RST/DEVID1 7:0 00h R01 DEVID2 7:0 01h (read only) R02 3:0 DEVREV 02h R3 7:0 PLL1 03h R4 7:0 PLL2 04h R5 5:0 PLL3 05h R6 3:0 PLL4 06h w LABEL DEFAULT RESET - ...
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WM8804 REGISTER BIT ADDRESS R7 1:0 PLL5 07h 5:4 R8 PLL6 08h w LABEL DEFAULT FREQMODE[1: FRACEN 1 3 MCLKDIV 0 CLKOUTDIV[1: CLKOUTSRC 1 4 CLKOUTDIS 1 5 FILLMODE 0 6 ALWAYSVALID 0 7 MCLKSRC 0 ...
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Production Data REGISTER BIT ADDRESS R9 SPDMODE 09h R10 7:0 INTMASK 0Ah w LABEL DEFAULT 0 SPDIFINMODE 1 MASK[7:0] 00000000 WM8804 DESCRIPTION S/PDIF Input Mode Select Selects the input circuit type for the receiver input CMOS input 1 ...
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WM8804 REGISTER BIT ADDRESS R11 INTSTAT 0Bh (read-only) R12 SPDSTAT 0Ch (read-only) w LABEL DEFAULT 0 - UPD_UNLOCK 1 - INT_INVALID 2 - INT_CSUD 3 - INT_TRANS_ERR 4 - UPD_NON_AUDIO 5 - UPD_CPY_N 6 - UPD_DEEMPH 7 - UPD_REC_FREQ 0 ...
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Production Data REGISTER BIT ADDRESS R13 RXCHAN1 0Dh (read-only) 5:4 7:6 R14 7:0 RXCHAN2 0Eh (read-only) R15 3:0 RXCHAN3 0Fh 5:4 (read-only) 7:6 R16 3:0 RXCHAN4 w LABEL DEFAULT 5:4 REC_FREQ -- [1:0] 6 UNLOCK - 0 CON/PRO 0 1 ...
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WM8804 REGISTER BIT ADDRESS 10h 5:4 (read-only) R17 RXCHAN5 11h (read-only) 3:1 7:4 R18 SPDTX1 12h 5:3 7:6 R19 7:0 SPDTX2 13h w LABEL DEFAULT CLKACU[1: MAXWL 1 RXWL[2:0] 000 ORGSAMP 0000 [3:0] 0 CON/PRO 0 1 AUDIO_N ...
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Production Data REGISTER BIT ADDRESS R20 3:0 SPDTX3 14h 5:4 7:6 R21 3:0 SPDTX4 15h 5:4 R22 SPDTX5 16h 3:1 7:4 w LABEL DEFAULT SRCNUM 0000 [3:0] CHNUM1[1:0] 00 CHNUM2[1:0] 00 FREQ[3:0] 0001 CLKACU[1: TXSRC 1 7 TXSTATSRC ...
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WM8804 REGISTER BIT ADDRESS R23 3:0 GPO0 17h R24 3:0 GPO1 18h R26 7:4 GPO2 1Ah R27 1:0 AIFTX 1Bh 3:2 R28 1:0 AIFRX 1Ch 3 LABEL DEFAULT GPO0[3:0] 0000 GPO1[3:0] 0111 GPO2[3:0] 0100 AIFTX_FMT[1:0] 10 AIFTX_WL[1:0] 01 ...
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Production Data REGISTER BIT ADDRESS R29 2:0 SPDRX1 1Dh w LABEL DEFAULT 5 AIFRX_LRP 0 6 AIF_MS 0 7 SYNC_OFF 0 READMUX 000 [2:0] 3 CONT 0 4 WITHFLAG 0 6 WL_MASK 0 7 SPD_192K_EN 1 WM8804 DESCRIPTION 2 Right, ...
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WM8804 REGISTER BIT ADDRESS R30 PWRDN 1Eh w LABEL DEFAULT 0 PLLPD 1 1 SPDIFRXPD 1 2 SPDIFTXPD 1 3 OSCPD 0 4 AIFPD 0 5 TRIOP 0 Production Data DESCRIPTION PLL Powerdown 0 = PLL enabled 1 = PLL ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Components for Hardware Control Mode w WM8804 PD, Rev 4.5, March 2009 63 ...
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WM8804 Figure 29 Recommended External Components for Software Control Mode w Production Data PD, Rev 4.5, March 2009 64 ...
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Production Data PACKAGE DIMENSIONS DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D ...
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... WM8804 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...