wm8803cdtv Wolfson Microelectronics plc, wm8803cdtv Datasheet
wm8803cdtv
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wm8803cdtv Summary of contents
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... CE W WM8803 FS CALCULATOR DATA BUFFER PLL CLOCK SELECTOR AMP AVDD AGND WM8803 Left, Right Justified 16/20/24/32 bit Word Lengths AUDIO PD DVDD DGND C & U ERROR CLKOUT BCLK AUDIO INTERFACE LRCLK SDATO SDIN Product Preview, September 2003, Rev 1.1 Copyright 2003 Wolfson Microelectronics plc ...
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WM8803 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT AND OUTPUT PIN CAPACITANCE................................................................... 6 DC CHARACTERISTICS............................................................................................... 6 ...
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Product Preview PIN CONFIGURATION XOUT 1 ERROR E/INT 9 AUDIO 10 UGPI 11 RXIN 12 w ORDERING INFORMATION DEVICE 24 XIN 23 SDIN WM8803SCDT/V SDATO 22 LRCLK ...
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WM8803 PIN DESCRIPTION PIN NAME 1 XOUT Analogue Output 2 ERROR Digital Output 5 3 Digital Input Digital Input Digital Input Digital Input Digital Input 8 DO Digital ...
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Product Preview ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Ele Characteristics at ...
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WM8803 ELECTRICAL CHARACTERISTICS INPUT AND OUTPUT PIN CAPACITANCE Test Conditions AVDD = DVDD = 25° 1MHz IN1 IN2 PARAMETER Input and Output Pin Capacitance Input pins Output pins Notes: 1. ...
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Product Preview SYSTEM TIMING REQUIREMENTS Test Conditions Ta = 25°C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER System Timing Information RXIN sampling frequency RXIN sampling frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN ...
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WM8803 Test Conditions Ta = 25°C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER CLKOUT to BCLK delay BCLK to SDATO delay ____ UGPI low-level pulse width Notes: 1. When setting the clock switching transition period signal ...
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Product Preview DEVICE DESCRIPTION _____ SYSTEM RESET ( PD) The system operates normally when PD is set to high level after applying a supply voltage of 2.7V(3.0V) or higher. Following power ON, the system is reset by setting PD to ...
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WM8803 The low power modes are listed in Table 1. MODE PDB AMPOPR (1) L × (2) 0 ( (5) 0 (6) 1 (7) 1 Table 1 Low Power Modes The table below lists the output ...
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Product Preview CLOCKS PLL (LPF) The WM8803 includes a VCO (voltage controlled oscillator) that can synchronize with data corresponding to sampling frequencies from 30k to 195kHz. The locking frequency is selected by setting PLLCK[1:0]. The VCO circuit can be stopped ...
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WM8803 OSCILLATOR AMPLIFIER (XIN AND XOUT) The following methods can be used to supply a clock signal to the internal oscillator amplifier. XIN XOUT (a) Oscillator element XIN XOUT (b) External clock signal Figure 5 XIN and XOUT Circuit Structures ...
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Product Preview The oscillator amplifier normally stops automatically when the PLL is locked, but continuous operation can be set by AMPCNT. Setting the WM8803 to continuous operation mode makes it possible to calculate the input sampling frequency when the PLL ...
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WM8803 Figure 6 Flowchart for CLKOUT Output Clock Narrow Band Operation The tables below show the output clocks in XIN and PLL clock source modes. PLLCK1 Table 6 ...
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Product Preview PLLCK1 Table 7 XIN Clock Source Mode Output Clocks Note: 1. XISEL2 = 1, PLL unlocked state or forced setting PLLCK1 Table 8 PLL Clock Source ...
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WM8803 RXIN XIN XOUT Figure 7 Master Clock System Diagram NOTES ON CLOCK SOURCE SWITCHING In states where the input fs calculation result is restricted by FLIMIT, if the WM8803 is switched by OCKSEL from the PLL locked state (oscillator ...
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Product Preview DATA INPUT AND OUTPUT BI-PHASE MARK MODULATED DIGITAL DATA INPUT (RXIN) The bi-phase mark modulated digital data is input through the RXIN pin. The RXIN pin supports TTL levels. This allows a 5V optical reception module to be ...
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WM8803 LRCLK BCLK SDIN MSB bits Figure 8 MSB First Left-justified Data Output (OFSEL [2:0] = 000) LRCLK BCLK 1 BCLK SDIN MSB 2 Figure Data Output (OFSEL ...
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Product Preview OUTPUT DATA FORMATS: SPECIAL MODE (SDATO) The output format of the audio data is set up after recovery In Special Mode the SDATO audio data range does not necessarily have to match the input data format. The output ...
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WM8803 LRCLK BCLK LSB -24 bit- SDATAO 28 bits Figure 13 Data Output Timing – NRZ Data LSB First Left-justified Output SERIAL AUDIO DATA INPUT FORMAT (SDIN) The SDIN pin is a serial digital audio data input that can accept ...
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Product Preview LRCLK BCLK 1 BCLK SDIN MSB 2 Figure Data Input LRCLK BCLK SDIN 1 2 MSB Figure 16 MSB First Right-justified Data Input OUTPUT DATA SWITCHING (SDIN, SDATO) The SDATO pin outputs ...
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WM8803 When XIN is set to be the clock source with OCKSEL, the PLL circuit will operate as long as PLL operation is not stopped by PDOWN[1:0] or PLLOPR. In this mode the state of the PLL circuit is always ...
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Product Preview status data delimiter bit 1. In this case, the parity error flag used for data recognized as PCM data will not be output. OTHER ERRORS Even when ERROR has gone low, the WM8803 always acquires bits 24 to ...
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WM8803 ERROR RECOVERY PROCESSING When the preamble B, M, and W are detected, the PLL circuit goes to the locked state and data demodulation starts. The SDATO output data starts on the first LRCLK edge after ERROR goes low. Internal ...
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Product Preview MICRO-CONTROLLER INTERFACE REGISTER OUTPUT (OPTICAL RECEIVER MODULE POWER DOWN EXAMPLE) This section describes an example in which UGPI outputs a micro-controller interface register, and how that signal is used as the power supply control signal for an optical ...
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WM8803 Figure 21 UGPI Output Usage Example (Data Input Switching Example) CLOCK SWITCHING TRANSITION PERIOD SIGNAL OUTPUT This section describes operation when UGPI is selected as the clock switching transition period signal. When there are changes to the PLL circuit ...
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Product Preview RXIN PLL Lock State XTAL Clock VCO Clock UGPI ERROR CLKOUT RXIN Digital Data PLL Lock State XTAL Clock VCO Clock UGPI ERROR CLKOUT Figure 22 Clock Switching Timing w Digital Data Unlocked Locked After PLL lock (a) ...
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WM8803 MICRO-CONTROLLER INTERFACE (E/INT, CE, CL, DI, DO) INTERRUPT OUTPUT (E/INT) The E/INT pin can be set to function as the micro-controller interface interrupt output using INTSEL. An interrupt is issued when a change occurs in the PLL lock state, ...
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Product Preview CCB ADDRESSES The address locations in Table 15 are those used to set the parameters, write data values and to read data values from the WM8803 over the micro-controller interface. The micro-controller interface data format conforms to that ...
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WM8803 I/O TIMING Hi-Z Figure 23 Input Timing Chart (Normal, Low Clock Hi-Z Figure 24 Input Timing Chart (Normal, High Clock ...
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Product Preview Hi-Z Figure 26 Output Timing Chart (Normal, High Clock) Note necessary to read DO0 with a separate port from DI. WRITE REGISTER TABLE The table below lists the ...
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WM8803 WRITE DATA DETAILED DOCUMENTATION DI7 DI6 MCKHFO PLLCK1 PLLCK0 DI15 DI14 XISEL3 XISEL2 XISEL1 Table 17 Input Register Function Settings 1: System Settings (0xE8) SYSRST: PDOWN[1:0]: PLLOPR: PLLCK[1:0]: MCKHFO: In the PLL locked state when switching from the 512fs ...
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Product Preview AMPOPR: AMPCNT: OCKSEL: XISEL[3:0]: w Oscillator amplifier operate/stop setting 0: Operate (initial value) 1: Stop Oscillator amplifier state setting 0: Automatically stop in the PLL locked state (initial value) 1: Always operate Clock source setting 0: Use the ...
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WM8803 DI7 DI6 FSSEL3 FSSEL2 DI15 DI14 0 RDTMUT RDTSTA Table 18 Input Register Function Settings 1: I/O Data Settings (0xE9) GPISEL: GPIDAT: FLIMIT: FS4XIN: FSSEL[3:0]: w DI5 DI4 DI3 FSSEL1 FSSEL0 FS4XIN DI13 DI12 DI11 RDTSEL 0 UGPI pin ...
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Product Preview FSSEL[3:0]: OFSEL[2:0]: RDTSEL: RDTSTA: RDTMUT: w Input data reception range setting (When FLIMIT = “1” and FS4XIN = “1”) 0000: 64k, 88.2k, 96k 128k, 176.4k, or 192kHz (initial value) 0001: 64kHz only 0010: 88.2kHz only 0011: 96kHz only ...
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WM8803 DI7 DI6 0 0 DI15 DI14 INTQSY INTCSF Table 19 Input Register Function Settings 1: Interrupt Settings (0xEA) INTOPF: INTSEL: INTERR: INTPCM : INTEMP: INTVFL : INTFSC: INTCSF: INTQSY: w DI5 DI4 DI3 DI13 DI12 DI11 ...
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Product Preview If E/INT is set up for high level output when an interrupts are generated with INTOPF , the high-level state will be maintained until the interrupt event output (address 0xEB) is read out. When that data has been ...
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WM8803 READ DATA DETAILED DOCUMENTATION DO7 DO6 OUTSQY OUTCSF OUTFSC Table 21 Output Register: Interrupt Data Output (0xEB) OUTERR: OUTPCM: OUTEMP: OUTVFL: OUTFSC: OUTCSF: OUTQSY: w DO5 DO4 DO3 OUTVFL OUTEMP ERROR output (Outputs the state when read ...
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Product Preview DO7 DO6 0 0 FSCAL2 8 Bit 7 Bit 6 16 Bit 15 Bit 14 24 Bit 23 Bit 22 32 Bit 31 Bit 30 40 Bit 39 Bit 38 48 Bit 47 Bit 46 Table 22 Output ...
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WM8803 DO7 DO6 Address Address 16 Track Track 24 Index Index 32 Minute Minute 40 Second Second 48 Frame Frame 56 Zero Zero 64 abs minute abs minute 72 abs second abs second 80 abs frame ...
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Product Preview SAMPLE APPLICATION The power supply pin de-coupling capacitors (0.1µF and 10µF) should be located as close as possible to the WM8803. Use ceramic and good quality electrolytic capacitors respectively, with good high-frequency characteristics for these components. Use a ...
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WM8803 RECOMMENDED EXTERNAL COMPONENTS CPU Interface NOTES: 1. AGND and DGND should be connected as close to the WM8803 as possible and C should be positioned as ...
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Product Preview RECOMMENDED EXTERNAL COMPONENTS VALUES SUGGESTED COMPONENT REFERENCE Ω 50k to 100k Ω 150 to 330 Ω 0.01µ to 0.1µ 33pF Over 1µF ...
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WM8803 PACKAGE DIMENSIONS DT: 24 PIN TSSOP (6.5 x 6.4 x 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 0.17 c 0.10 D 6.4 e ...
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... Product Preview IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’ ...