wm8803cdtv Wolfson Microelectronics plc, wm8803cdtv Datasheet - Page 21

• Manufacturer Part Number: wm8803cdtv
• Description: Digital Audio Interface Receiver
• Manufacturer: Wolfson Microelectronics plc

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Figure 15 I
Figure 16 MSB First Right-justified Data Input
w
LRCLK
LRCLK
BCLK
BCLK
SDIN
SDIN
2
S Data Input
MSB
1 BCLK
1
OUTPUT DATA SWITCHING (SDIN, SDATO)
The SDATO pin outputs the demodulated data when the PLL circuit is locked and the SDIN input
data when the PLL circuit is unlocked. Switching between SDIN and SDATO is performed
automatically according to the locked/unlocked state of the PLL circuit. When XIN is the clock
source, input data synchronized with the CLKOUT, BCLK, and LRCLK clocks as the SDIN input data.
The SDIN input data can be output from SDATO by setting RDTSTA regardless of the PLL circuit
locked/unlocked state. In this case, the CLKOUT, BCLK, and LRCLK clocks will also be switched to
the XIN clock source. The switch occurs in synchronization with the LRCLK edge that follows the
setting of the RDTSTA.
The SDATO output data can be forcibly muted by setting RDTMUT. The muting processing is started
in synchronization with the LRCLK edge that follows the setting of the RDTMUT.
The SDATO output can be muted in the PLL locked state by setting RDTSEL.
These settings have the following priority order: RDTSEL < RDTSTA < RDTMUT.
2
MSB
1
3
2
CHANNEL
3
CHANNEL
16 to 24 bits
LEFT
LEFT
16,20,24 bits
n-2 n-1
n-2 n-1
LSB
n
LSB
n
1/fs
1/fs
MSB
1 BCLK
1
MSB
1
2
2
3
CHANNEL
RIGHT
3
CHANNEL
16 to 24 bits
RIGHT
16,20,24 bits
n-2 n-1
n-2 n-1
PP Rev 1.1 September 2003
n
LSB
LSB
n
WM8803
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