a54sx72a Actel Corporation, a54sx72a Datasheet

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... Std, –1, –2, – 208 208 100, 144 100, 144 – – 144 144, 256 – – Programming Technology A54SX32A A54SX72A 32,000 72,000 48,000 108,000 2,880 6,036 1,800 4,024 1,080 2,012 1,980 4,024 249 360 3 3 ...

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... A54SX16A 2 Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Notes: 1. For more information about the CQFP package options, refer to the 2. All –3 speed grades have been discontinued. Device Resources 208-Pin 100-Pin ...

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... Contact your Actel Sales representative for more information on availability. A54SX16A A54SX32A C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,M C,I,M C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,M C,M,B C,M,B SX-A Automotive Family FPGAs HiRel SX-A Family FPGAs Std –1 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ SX-A Automotive Family FPGAs HiRel SX-A Family FPGAs v5.3 SX-A Family FPGAs A54SX72A C,I,A,M C,I,A,M C,I,A,M C,M,B C,M,B datasheet. datasheet. –2 –3 ✓ Discontinued ✓ Discontinued datasheet. datasheet. iii ...

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SX-A Family FPGAs Table of Contents General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Routing Tracks Tungsten Plug Contact Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3. Figure 1-1 • SX-A Family Interconnect Elements SX-A Family Architecture The SX-A family’ ...

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SX-A Family FPGAs Logic Module Design The SX-A family architecture is described as a “sea-of- modules” architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect ...

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Routing Resources The routing and interconnect resources of SX-A devices are in the top two metal layers above the logic modules (Figure 1-1 on page 1-1), providing optimal use of silicon, thus enabling the entire floor of the device to ...

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SX-A Family FPGAs Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters 1 -4 DirectConnect • No Antifuses • 0.1 ns Maximum Routing Delay FastConnect • One Antifuse • ...

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... For more information on how to use quadrant clocks in the A54SX72A device, refer to the in Actel’s Antifuse Devices RT54SX72S Quadrant Clocks The CLKA, CLKB, and QCLK circuits for A54SX72A as well as the macros supported are shown in page 1-6. Note that bidirectional clock buffers are only available in A54SX72A ...

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... SX-A Family FPGAs Quadrant 2 QCLKINT (to array) Quadrant 0 QCLKINT (to array) Figure 1-9 • SX-A QCLK Architecture Figure 1-10 • A54SX72A Routed Clock and QCLK Buffer QCLKBUFS 4 Quadrant 3 5:1 5:1 QCLKINT (to array) 4 Quadrant 1 5:1 5:1 QCLKINT (to array) OE From Internal Logic Clock Network From Internal Logic CLKBUF QCLKBUF CLKBUFI QCLKBUFI CLKINT ...

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Other Architectural Features Technology The Actel SX-A family is implemented on a high-voltage, twin-well CMOS process using 0.22 μ / 0.25 μ design rules. The metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier ...

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... Supply Ramp Rate 0.25 V/μs 0.025 V/μs μs Units A54SX08A 10 A54SX16A 10 A54SX32A 10 A54SX72A are reached. which the I/Os behave according to the user’s design for and V do not an SX-A device at room temperature for various ramp-up CCA CCI rates. The data reported assumes a linear ramp-up profile to 2 ...

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Boundary-Scan Testing (BST) All SX-A devices are IEEE 1149.1 compliant and offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through the special JTAG pins (TMS, TDI, TCK, TDO, ...

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... USERCODE IDCODE HighZ CLAMP Diagnostic BYPASS Reserved Table 1-8 • JTAG Instruction Code Device Process A54SX08A 0.22 µ A54SX16A 0.22 µ 0.25 µ A54SX32A 0.2 2µ 0.25 µ A54SX72A 0.22 µ 0.25 µ Binary Code 00000 00001 00010 00011 00100 01110 01111 10000 11111 All others Revision Bits 31-28 0 ...

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Probing Capabilities SX-A devices also provide an internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II diagnostic hardware is used to control the TDI, TCK, TMS, and TDO pins to select the desired nets for ...

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SX-A Family FPGAs SX-A Probe Circuit Control Pins SX-A devices contain internal probing circuitry that provides built-in access to every node in a design, enabling 100% real-time observation and analysis of a device's internal logic nodes without design iteration. The ...

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Design Environment The SX-A family of FPGAs is fully supported by both Actel ® Libero Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, integrating design tools while guiding the user through ...

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... SX-A Family FPGAs Related Documents Application Notes Global Clock Networks in Actel’s Antifuse Devices http://www.actel.com/documents/GlobalClk_AN.pdf Using A54SX72A and RT54SX72S Quadrant Clocks http://www.actel.com/documents/QCLK_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Actel eX, SX-A, and RTSX-S I/Os http://www.actel.com/documents/AntifuseIO_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications http://www ...

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... QCLKA/B/C/D, I/O Quadrant Clock and D These four pins are the quadrant clock inputs and are only used for A54SX72A with and D corresponding to bottom-left, bottom-right, top-left, and top-right quadrants, respectively. They are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, LVCMOS2, 3 ...

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...

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... V Power Supply Range (V ) CCI Typical SX-A Standby Current Table 2-3 • Typical Standby Current for SX-A at 25°C with V Product A54SX08A A54SX16A A54SX32A A54SX72A Table 2-4 • Supply Voltages V CCA 2.5 V 2.5 V Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant. Parameter " ...

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SX-A Family FPGAs Electrical Specifications Table 2-5 • 3.3 V LVTTL and 5 V TTL Electrical Specifications Symbol Parameter Minimum OH CCI Minimum CCI ...

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PCI Compliance for the SX-A Family The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-7 • DC Specifications (5 V PCI Operation) Symbol Parameter V Supply ...

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SX-A Family FPGAs Table 2-8 • AC Specifications (5 V PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current Low OL(AC) (Test Point) I Low Clamp Current CL slew Output Rise Slew Rate R slew ...

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Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 200 MAX Spec 150.0 100.0 50.0 0.0 0 0.5 –50 MIN Spec –100.0 –150.0 –200.0 ...

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SX-A Family FPGAs Table 2-10 • AC Specifications (3.3 V PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current Low OL(AC) (Test Point) I Low Clamp Current CL I High Clamp Current CH slew Output ...

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Figure 2-2 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 150 MAX Spec 100.0 50.0 0.0 0 0.5 –50 MIN Spec –100.0 –150.0 Figure 2-2 ...

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SX-A Family FPGAs Power Dissipation A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating ...

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... EQCR Dedicated array clocks – variable (C ) EQHV Dedicated array clocks – fixed (C ) EQHF Routed array clock A54SX08A A54SX16A 1.70 pF 2.00 pF 1.50 pF 1.50 pF 1.30 pF 1.30 pF 7.40 pF 7.40 pF 1.05 pF 1.05 pF 0.85 pF 0.85 pF 30.00 pF 55.00 pF 35.00 pF 50.00 pF v5.3 SX-A Family FPGAs A54SX32A A54SX72A 2.00 pF 1.80 pF 1.30 pF 1.50 pF 1.30 pF 1.30 pF 7.40 pF 7.40 pF 1.05 pF 1.05 pF 0.85 pF 0.85 pF 110.00 pF 240.00 pF 90.00 pF 310.00 pF 2-9 ...

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SX-A Family FPGAs Guidelines for Estimating Power The following guidelines are meant to represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation: Logic Modules (m) = 20% of modules Inputs Switching (n) = ...

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... Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Notes: 1. The A54SX08A PQ208 has no heat spreader. 2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A – θ ...

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SX-A Family FPGAs Theta-JA Junction-to-ambient thermal resistance ( has little relevance in actual performance of the product in real application. It should be employed with caution but is useful for comparing the thermal performance of one package to another. A ...

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To determine the heat sink's thermal performance, use the following equation: where: θ = 0.37°C thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer θ = thermal ...

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... Load) I/O Module t = 0.6 ns INYH Hardwired Clock t = 1.8 ns HCKH Note: *Values shown for A54SX72A, –2, worst-case commercial conditions PCI with standard place-and-route. Figure 2-3 • SX-A Timing Model Sample Path Calculations Hardwired Clock External Setup = (t INYH = 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns Clock-to-Out (Pad-to-Pad HCKH = 1 ...

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Output Buffer Delays 50% 50% GND V OH 1.5 V Out 1 DLH Figure 2-4 • Output Buffer Delays AC Test Loads Load 1 (Used to measure propagation delay) To the Output Under ...

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SX-A Family FPGAs Input Buffer Delays PAD INBUF 1 Out 50% GND t t INY INY Figure 2-6 • Input Buffer Delays Cell Timing Characteristics D t SUD CLK Q CLR PRESET ...

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Timing Characteristics Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after ...

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SX-A Family FPGAs Timing Characteristics Table 2-14 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC t ...

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Table 2-14 • A54SX08A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...

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SX-A Family FPGAs Table 2-15 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-16 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse ...

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SX-A Family FPGAs Table 2-17 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-18 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad, Z ...

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SX-A Family FPGAs Table 2-19 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 1 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...

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Table 2-20 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...

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SX-A Family FPGAs Table 2-21 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect ...

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Table 2-21 • A54SX16A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...

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SX-A Family FPGAs Table 2-22 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-23 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse ...

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SX-A Family FPGAs Table 2-24 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-25 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad, Z ...

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SX-A Family FPGAs Table 2-26 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...

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Table 2-27 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...

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SX-A Family FPGAs Table 2-28 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect ...

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Table 2-28 • A54SX32A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...

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SX-A Family FPGAs Table 2-29 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-30 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse ...

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SX-A Family FPGAs Table 2-31 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...

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Table 2-32 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad, Z ...

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SX-A Family FPGAs Table 2-33 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...

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Table 2-34 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...

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... SX-A Family FPGAs Table 2-35 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect Routing Delay, Fast Connect Routing Delay RD1 Routing Delay RD2 ...

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... Table 2-35 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to Y High 5 V TTL INYH t Input Data Pad to Y Low 5 V TTL ...

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... SX-A Family FPGAs Table 2-36 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low HPWL ...

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... Table 2-36 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse Width High QPWH t Minimum Pulse Width Low QPWL t Maximum Skew (Light Load) ...

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... SX-A Family FPGAs Table 2-37 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low HPWL ...

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... Table 2-37 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse Width High QPWH t Minimum Pulse Width Low QPWL t Maximum Skew (Light Load) ...

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... SX-A Family FPGAs Table 2-38 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low HPWL ...

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... Table 2-38 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse Width High QPWH t Minimum Pulse Width Low QPWL t Maximum Skew (Light Load) ...

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... SX-A Family FPGAs Table 2-39 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad ENZL t Data-to-Pad L—low slew ...

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... Table 2-40 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ENHZ ...

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... SX-A Family FPGAs Table 2-41 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ...

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Package Pin Assignments 208-Pin PQFP 208 1 Figure 3-1 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v5.3 SX-A Family FPGAs 3-1 ...

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... I CCA I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 I/O I I/O 60 GND GND CCA CCA GND GND 63 I/O I/O 64 TRST, I/O TRST, I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 v5.3 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI CCA CCA CCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND GND ...

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... I/O I/O 127 I/O I/O 128 I/O I/O 129 I/O I/O 130 I/O I/O 131 I/O I/O 132 V V 133 CCI CCI I/O I/O 134 I/O I/O 135 I/O I/O 136 I/O I/O 137 TDO, I/O 138 I/O I/O 139 GND GND 140 v5.3 SX-A Family FPGAs 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA CCI CCI CCI NC I/O I/O I/O I/O I/O I/O I/O I/O NC ...

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... CCI CCI I/O I/O 200 I/O I/O 201 I/O I/O 202 I/O I/O 203 I/O I/O 204 I/O I/O 205 I/O I/O 206 I/O I/O 207 I/O I/O 208 I/O I/O I/O I/O v5.3 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKA CLKA CLKB CLKB CLKB GND GND GND CCA CCA CCA GND GND GND PRA, I/O PRA, I/O PRA, I/O ...

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TQFP 100 1 Figure 3-2 • 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 100-Pin TQFP v5.3 SX-A Family FPGAs 3-5 ...

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SX-A Family FPGAs 100-TQFP A54SX08A A54SX16A Pin Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 TMS TMS CCI 9 GND GND ...

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A54SX08A A54SX16A Pin Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O ...

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SX-A Family FPGAs 144-Pin TQFP 144 1 Figure 3-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html 144-Pin TQFP v5.3 ...

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TQFP A54SX08A A54SX16A Pin Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 TMS TMS ...

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SX-A Family FPGAs 144-Pin TQFP A54SX08A A54SX16A Pin Number Function Function 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I CCA CCA CCI 81 GND GND 82 I/O I/O 83 I/O ...

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TQFP 176 1 Figure 3-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 176-Pin TQFP v5.3 SX-A Family FPGAs 3-11 ...

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SX-A Family FPGAs 176-Pin TQFP Pin A54SX32A Number Function Number 1 GND 2 TDI, I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 TMS 11 V CCI 12 I/O 13 I/O 14 I/O ...

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TQFP Pin A54SX32A Number Function 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 I/O 152 CLKA 153 CLKB 154 NC 155 GND 156 V CCA 157 PRA, I/O 158 I/O 159 I/O 160 I/O ...

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SX-A Family FPGAs 329-Pin PBGA Figure 3-5 • 329-Pin PBGA (Top View) Note For ...

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PBGA Pin A54SX32A Pin Number Function Number A1 GND AA15 A2 GND AA16 A3 V AA17 CCI A4 NC AA18 A5 I/O AA19 A6 I/O AA20 A7 V AA21 CCI A8 NC AA22 A9 I/O AA23 A10 I/O AB1 ...

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SX-A Family FPGAs 329-Pin PBGA Pin A54SX32A Number Function Number D11 V CCA D12 NC D13 I/O D14 I/O D15 I/O D16 I/O D17 I/O D18 I/O D19 I/O D20 I/O D21 I/O D22 I/O D23 I CCI ...

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PBGA Pin A54SX32A Number Function V22 I/O V23 I/O W1 I/O W2 I/O W3 I/O W4 I/O W20 I/O W21 I/O W22 I/O W23 I/O Y3 I/O Y4 GND Y5 I/O Y6 I/O Y7 I/O ...

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SX-A Family FPGAs 144-Pin FBGA Figure 3-6 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html ...

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FBGA A54SX08A A54SX16A Pin Number Function Function A1 I/O I/O A2 I/O I/O A3 I/O I/O A4 I/O I CCA CCA A6 GND GND A7 CLKA CLKA A8 I/O I/O A9 I/O I/O A10 I/O I/O ...

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SX-A Family FPGAs 144-Pin FBGA A54SX08A A54SX16A Pin Number Function Function G1 I/O I/O G2 GND GND G3 I/O I/O G4 I/O I/O G5 GND GND G6 GND GND G7 GND GND CCI G9 I/O I/O G10 ...

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FBGA Figure 3-7 • 256-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html ...

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... C11 I/O C12 I/O C13 CLKB C14 I/O C15 I/O C16 I/O D1 I/O D2 I/O D3 GND D4 GND D5 I/O D6 GND D7 I/O D8 PRA, I/O I/O D9 I/O D10 I/O D11 I/O D12 V D13 CCA I/O D14 I/O D15 I/O D16 I/O E1 I/O E2 I/O E3 GND E4 I/O E5 I/O E6 TDI, I/O E7 GND E8 I/O E9 I/O E10 v5.3 256-Pin FBGA A54SX32A A54SX72A Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKA CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O PRA, I/O I/O I/O QCLKD I/O I/O I/O NC I/O I/O ...

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... I/O J8 I/O J9 I/O J10 V J11 CCI GND J12 GND J13 GND J14 GND J15 V J16 CCI I/O K1 GND K2 I CCA v5.3 SX-A Family FPGAs 256-Pin FBGA A54SX32A A54SX72A Function Function I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA TRST, I/O TRST, I/O I/O I/O I CCI CCI CCI GND GND GND GND GND ...

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... CCI CCI I/O N1 I/O N2 I/O N3 I/O N4 I/O N5 I/O N6 I/O N7 I/O N8 I/O N9 I/O N10 I/O N11 V N12 CCI CCI V N13 CCI CCI V N14 CCI CCI V N15 CCI CCI I/O N16 I/O P1 I/O P2 I/O P3 I/O P4 I/O P5 I/O P6 I/O P7 I/O P8 I/O P9 I/O P10 I/O P11 QCLKA P12 PRB, I/O P13 I/O P14 v5.3 256-Pin FBGA A54SX16A A54SX32A A54SX72A Function Function Function I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

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... R13 I/O I/O R14 I/O I/O R15 GND GND R16 GND GND T1 GND GND T2 I/O I/O T3 I/O I I/O T5 I/O I/O T6 I/O I/O T7 I/O I/O T8 I/O I CCA CCA T10 I/O I/O T11 I/O I/O T12 NC I/O T13 I/O I/O T14 I/O I/O T15 TDO, I/O TDO, I/O T16 GND GND A54SX72A Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK QCLKB I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O V CCA I/O I/O I/O I/O I/O TDO, I/O GND v5.3 SX-A Family FPGAs 3-25 ...

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SX-A Family FPGAs 484-Pin FBGA 11121314 15161718 19 20212223 242526 ...

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... I/O AB25 NC* I/O AB26 NC* I/O AC1 I/O I/O AC2 I/O I/O AC3 I/O I/O AC4 NC* I/O AC5 V V CCI CCI AC6 I/O I/O AC7 V V CCI CCI AC8 I/O I/O v5.3 SX-A Family FPGAs 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function AC9 I/O I/O AC10 I/O I/O AC11 I/O I/O AC12 I/O QCLKA AC13 I/O I/O AC14 I/O I/O AC15 I/O I/O AC16 I/O I/O AC17 I/O I/O AC18 I/O I/O AC19 I/O I/O AC20 V V CCI ...

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... I/O AF24 NC* I/O AF25 NC* NC AF26 NC* I/O B4 NC* I/O B5 NC* I/O B6 I/O I/O B7 I/O I/O B8 I/O I/O B9 I/O I/O v5.3 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function B10 I/O I/O B11 NC* I/O B12 NC* I/O B13 V V CCI CCI B14 CLKA CLKA B15 NC* I/O B16 NC* I/O B17 I/O I/O B18 V V CCI CCI B19 I/O I/O B20 I/O I/O B21 ...

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... CCI CCI E26 GND GND CCI CCI F2 NC* I/O F3 NC* I/O F4 I/O I/O F5 I/O I/O F22 I/O I/O F23 I/O I/O F24 I/O I/O F25 I/O I/O F26 NC* I/O v5.3 SX-A Family FPGAs 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function G1 NC* I/O G2 NC* I/O G3 NC* I/O G4 I/O I/O G5 I/O I/O G22 I/O I/O G23 V V CCA CCA G24 I/O I/O G25 NC* I/O G26 NC* I/O H1 NC* I/O H2 NC* I/O ...

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... N22 V V CCA CCA N23 I/O I/O N24 I/O I/O N25 I/O I/O N26 NC NC* I/O P2 NC* I/O P3 I/O I/O v5.3 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function P4 I/O I CCA CCA P10 GND GND P11 GND GND P12 GND GND P13 GND GND P14 GND GND P15 GND GND ...

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... GND GND U17 GND GND U22 I/O I/O U23 I/O I/O U24 I/O I/O U25 V V CCI CCI U26 I/O I/O V1 NC* I/O Note: *These pins must be left floating on the A54SX32A device. 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function V2 NC* I/O V3 I/O I/O V4 I/O I/O V5 I/O I/O V22 V V CCA CCA V23 I/O I/O V24 I/O I/O V25 NC* ...

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...

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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v5.2 –3 speed grades have been discontinued. (June 2006) The ...

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SX-A Family FPGAs Previous Version Changes in Current Version ( v4.0 Table 2-12 was updated. (continued) The was updated. The "Sample Path Calculations" Table 2-13 was updated. Table 2-13 was updated. All timing tables were updated. v3.0 The ...

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... Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information ...

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... Actel and the Actel logo are registered trademarks of Actel Corporation. Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. ...