mr4a16b Everspin Technologies, Inc, mr4a16b Datasheet - Page 10

• Manufacturer Part Number: mr4a16b
• Description: 1m X 16 Mram
• Manufacturer: Everspin Technologies, Inc

Everspin Technologies © 2010
Timing Specifications
1
2
3
All write cycle timings are referenced from the last valid address to the first transition address.
Parameter
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Enable to end of write (G high)
Enable to end of write (G low)
Data valid to end of write
Data hold time
Write recovery time
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
UB, LB (BYTE ENABLE)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
D (DATA IN)
2
3
Figure 3.5 Write Cycle Timing 2 (E Controlled)
Table 3.5 Write Cycle Timing 2 (E Controlled)
t
AVEL
t
AVEH
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVEL
AVEH
AVEH
ELEH
ELWH
ELEH
ELWH
DVEH
EHDX
EHAX
t
AVAV
Hi-Z
Document Number: MR4A16B Rev. 5, 4/2010
Min
35
0
20
20
15
15
10
0
12
t
t
ELEH
ELWH
Data Valid
t
DVEH
1
1
Max
-
-
-
-
-
-
-
-
-
t
EHDX
MR4A16B
t
EHAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns