gal18v10b-7lp Lattice Semiconductor Corp., gal18v10b-7lp Datasheet - Page 11

• Manufacturer Part Number: gal18v10b-7lp
• Description: Gal18v10 Gal Data Sheets High Performance E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL18V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
Power-Up Reset
Input/Output Equivalent Schematics
PIN
(Vref Typical = 3.2V)
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Typical Input
Vcc
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
Vref
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc
Vcc
Vcc (min.)
11
t
pr
conditions must be met to provide a valid power-up reset of the
device. First, the V
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
Specifications GAL18V10
t
wl
Tri-State
Control
t
su
Feedback
CC
rise must be monotonic. Second, the clock
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
(Vref Typical = 3.2V)
PIN
PIN