gal18v10b-7lp Lattice Semiconductor Corp., gal18v10b-7lp Datasheet - Page 9

• Manufacturer Part Number: gal18v10b-7lp
• Description: Gal18v10 Gal Data Sheets High Performance E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
LOGIC
ARRAY
f
LOGIC
ARRAY
max with No Feedback
t
t
su +
su
t
h
300Ω
300Ω
300Ω
R
-15/-20
∞
∞
-7/-10
1
REGISTER
REGISTER
CLK
CLK
390Ω
390Ω
390Ω
390Ω
390Ω
R
2ns 10% – 90%
3ns 10% – 90%
2
t
GND to 3.0V
t
See Figure
su+
co
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
9
FROM OUTPUT (O/Q)
UNDER TEST
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
*C
Specifications GAL18V10
f
L
max with Internal Feedback 1/(
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
t
cf
t
+5V
pd
REGISTER
CLK
R
1
t
C *
su+
L
t
TEST POINT
cf)