gal20vp8 Lattice Semiconductor Corp., gal20vp8 Datasheet
gal20vp8
Related parts for gal20vp8
gal20vp8 Summary of contents
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... Memory Address, Data and Control Circuits — DMA Control • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL20VP8, with 64 mA drive capability and 15 ns maximum propagation delay time is ideal for Bus and Memory control appli- cations. The GAL20VP8 is manufactured using Lattice ...
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... GAL20VP8 Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA Part Number Description GAL20VP8B Device Name Speed (ns Low Power Power Ordering # 115 GAL20VP8B-15LP 115 GAL20VP8B-15LJ 115 GAL20VP8B-25LP 115 GAL20VP8B-25LJ _ XXXXXXXX Specifications GAL20VP8 Package 24-Pin Plastic DIP ...
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... These two global and 24 individual architecture bits define all possible con- figurations in a GAL20VP8. The information given on these archi- tecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits ...
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... OE XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20VP8 Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB LSB DIP (PLCC) Package Pinouts PTD 2703 .... 2630, 2631 .... Byte1 Byte0 5 Specifications GAL20VP8 24(28) 2640 23(27) OLMC 22(26) XOR-2560 AC1-2632 AC2-2706 OLMC 21(25) XOR-2561 AC1-2633 AC2-2707 OLMC 20(24) XOR-2562 AC1-2634 AC2-2708 OLMC 19(23) XOR-2563 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20VP8 All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1(2) and 12(14) are always available as data inputs into the AND array. ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB LSB Specifications GAL20VP8 DIP (PLCC) Package Pinouts PTD 2703 .... 2630, 2631 .... Byte1 Byte0 7 24(28) 2640 23(27) OLMC 22(26) XOR-2560 AC1-2632 AC2-2706 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20VP8 Pins 1(2) and 12(14) are always available as data inputs into the AND array. The center two macrocells (pins 17(20) & 19(23)) can- not be used in the input configuration. ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB LSB Specifications GAL20VP8 DIP (PLCC) Package Pinouts PTD 2703 .... 2630, 2631 .... Byte1 Byte0 9 24(28) 2640 23(27) OLMC 22(26) XOR-2560 AC1-2632 AC2-2706 ...
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... IL 3. MAX. Vin = MAX. Vin = 0.5V CC OUT = 0. 3. 15MHz Outputs Open = Specifications GAL20VP8 ) ............................... MIN. TYP. 4 — Vss – 0.5 2.0 — — — — — — — — 2.4 — IH — ...
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... Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL20VP8 Over Recommended Operating Conditions MAXIMUM* UNITS COM COM -25 -15 MIN. MAX. MIN. MAX. 3 ...
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... Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL20VP8 INPUT or I/O FEEDBACK CLK VALID INPUT REGISTERED t pd OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 12 VALID INPUT ...
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... See Figure FROM OUTPUT (O/Q) UNDER TEST 500 50pF 500 50pF 500 50pF 500 5pF 500 5pF 13 Specifications GAL20VP8 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + INCLUDES TEST FIXTURE AND PROBE CAPACITANCE ...
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... This provides a typical hysteresis of 200mV between positive and negative transitions of the inputs. Bulk Erase Mode All eight outputs of the GAL20VP8 are capable of driving 64 mA loads when driving low and 32 mA loads when driving high. Near symmetrical high and low output drive capability provides small skews between high-to-low and low-to-high output transitions ...
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... Q - OUTPUT nous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20VP8. First, the V rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of eration, avoid clocking the device until all input and feedback path setup times have been met ...
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... Delta Tco Outputs Switching 0 -0.25 -0.5 -0.75 RISE -1 FALL -1. Number of Outputs Switching Delta Tco vs Output Loading 100 150 200 250 300 16 Specifications GAL20VP8 Normalized Tsu vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.50 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 125 -55 - Temperature (deg. C) Switching RISE ...
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... Typical AC and DC Characteristic Diagrams Vol vs Iol 0.5 0.4 0.3 0.2 0.1 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input) 3 2.5 2 1.5 1 0.5 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL20VP8 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Input Clamp (Vik ...