gal22lv10 Lattice Semiconductor Corp., gal22lv10 Datasheet
gal22lv10
Manufacturer Part Number
gal22lv10
Description
Low Voltage E2 Cmos Pld Generic Array Logic? Gal22lv10 Gal
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.GAL22LV10.pdf
(19 pages)
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• HIGH PERFORMANCE E
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The GAL22LV10D, at 4 ns maximum propagation delay time, pro-
vides the highest speed performance available in the PLD market.
The GAL22LV10C can interface with both 3.3V and 5V signal levels.
The GAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
Electrically Erasable (E
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22lv10_06
Features
Description
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— 100% Functional Testability
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
(GAL22LV10C)
®
Advanced CMOS Technology
2
CMOS process, which combines CMOS with
2
) floating gate technology. High speed erase
2
CMOS
®
TECHNOLOGY
1
Functional Block Diagram
Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
I
NC
I
I
I
I
I
I
11
5
7
9
12
4
GAL22LV10
Low Voltage E
14
2
Top View
GAL22LV10
PLCC
Generic Array Logic™
28
16
PRESET
RESET
10
12
14
16
16
12
10
14
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
26
18
25
23
21
19
2
CMOS PLD
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
August 2006
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
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