f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet - Page 10

• Manufacturer Part Number: f25l32qa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual And Quad
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Quad Enable (QE)
When the Quad Enable bit is reset to “0” (factory default), WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO
during standard and Dual SPI operation if the WP and HOLD
pins are tied directly to the V
Elite Semiconductor Memory Technology Inc.
TOP
2
and SIO
Protection Level
Upper 1/64
Upper 1/32
Upper 1/16
All Blocks
Upper 1/8
Upper 1/4
Upper 1/2
3
are enabled. (The QE should never be set to “1”
0
DD
or V
SS
.)
BP2
0
0
0
0
1
1
1
1
Status Register Bit
Table 3: F25L32QA Block Protection Table
BP1
0
0
1
1
0
0
1
1
(Preliminary)
BP0
0
1
0
1
0
1
0
1
Block Protection Lock-Down (BPL)
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
WP pin driven low (V
WP pin is driven high (V
Block Range
Block 60~63
Block 62~63
Block 56~63
Block 48~63
Block 32~63
Block 0~63
Block 63
None
Protected Memory Area
Publication Date: Jan. 2009
Revision: 0.2
3C0000H –3FFFFFH
000000H –3FFFFFH
3F0000H –3FFFFFH
3E0000H –3FFFFFH
380000H –3FFFFFH
300000H –3FFFFFH
200000H –3FFFFFH
IH
IL
Address Range
), enables the Block-Protection-
), the BPL bit has no effect and its
None
F25L32QA
10/42