f25l32qa Elite Semiconductor Memory Technology Inc., f25l32qa Datasheet - Page 29

• Manufacturer Part Number: f25l32qa
• Description: 3v Only 32 Mbit Serial Flash Memory With Dual And Quad
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Deep Power Down (DP)
The Deep Power Down instruction is for minimizing power
consumption (the standby current is reduced from I
This instruction is initiated by executing an 8-bit command, B9H,
and then CE must be driven high. After CE is driven high, the
device will enter to deep power down within the duration of T
Release from Deep Power Down (RDP) and Read Electronic-Signature (RES)
The
Electronic-Signature instruction is a multi-purpose instruction.
The instruction can be used to release the device from the deep
power down status. This instruction is initiated by driving CE
low and executing an 8-bit command, ABH, and then drive CE
high. See Figure 26 for RDP instruction. Release from the deep
power down will take the duration of T
resume normal operation and other instructions are accepted.
The instruction also can be used to read the 8-bit Electronic-
Signature of the device on the SO pin. It is initiated by driving
Elite Semiconductor Memory Technology Inc.
CE must remain high during T
Figure 25: Deep Power Down Instruction
Release
form
SCK
CE
SI
MODE0
MODE3
Deep
RES1
MSB
Power
.
0
RES1
1
before the device will
Down
2
3
B9
SB1
(Preliminary)
and
4
to I
5
SB2
Read
.).
6
DP
.
7
Once the device is in deep power down status, all instructions will
be ignored except the Release from Deep Power Down
instruction (RDP) and Read Electronic Signature instruction
(RES). The device always power-up in the normal operation with
the standby current (I
Down instruction.
dummy bytes. The Electronic-Signature byte is then output from
the device. The Electronic-Signature can be read continuously
until CE go high. See Figure 27 for RES sequence. After
driving CE high, it must remain high during for the duration of
T
other instructions are accepted.
The instruction is executed while an Erase, Program or WRSR
cycle is in progress is ignored and has no effect on the cycle in
progress. In OTP mode, user also can execute RES to confirm
the status of OTP.
CE low and executing an 8-bit command, ABH, followed by 3
RES2
Standard Current
, and then the device will resume normal operation and
T
DP
Deep Power Down Current
SB1
Publication Date: Jan. 2009
Revision: 0.2
). See Figure 25 for the Deep Power
(I
SB2
)
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