uc1602i-pp-m ETC-unknow, uc1602i-pp-m Datasheet - Page 22

• Manufacturer Part Number: uc1602i-pp-m
• Description: Single-chip, Ultra-low Power Passive Matrix Lcd Controller-driver
• Manufacturer: ETC-unknow

U
High-Voltage Mixed-Signal IC
R
T
UC1602I has two different types of Reset:
Power-ON-Reset is performed right after V
connected to power. Power-On-Reset will first
wait for about 12mS, depending on the time
required for V
System Reset .
System Reset can also be activated by software
command or by connecting RST pin to ground.
In the following discussions, Reset means
System Reset .
R
When UC1602I enters RESET sequence:
•
•
•
•
Refer to Control Registers for details of control
flags and their default values. Refer to Pin
Description for configuration pin definitions.
When RS=1, only status read command is
processed by UC106. All other commands are
ignored.
Once entered Reset mode, all control registers
will be reset to their default values and capacitors
will be discharged. In general it is necessary to
set up control registers before transition out of
the Reset mode.
O
UC1602I has three operating modes (OM):
20
Reset, Normal, Sleep.
YPES OF
ESET
PERATION
Power-ON-Reset and System-Reset .
ESET
Draining Circuit
LTRA
Host Interface
Charge Pump
LCD Drivers
All non-pin configurable control registers will
be reset to their default values.
All pin configurable control registers will be
reset according to their configuration pins.
Operation mode will be “Reset”
System Status bits RS and BZ will stay as
“1” until the Reset process is completed (for
a duration of 3~5uS).
S
Mode
Clock
TATUS
OM
& P
R
C
Table 11: Operating Modes
ESET
M
HIP
ODES
DD
OWER
to stabilize, and then trigger the
Reset
Active
OFF
OFF
OFF
M
ON
00
ANAGEMENT
Sleep Normal
Active
OFF
OFF
OFF
OFF
10
Active
OFF
ON
ON
ON
11
DD1
is
C
Two commands will initiate OM transitions:
When DC[2] is modified by Set Display Enable ,
OM will be updated automatically. There is no
other action required to enter power saving mode.
For maximum energy utilization, Sleep mode is
designed to retain charges stored in external
capacitors C
capacitors, use Reset command to activate the
on-chip draining circuit.
OM changes are synchronized with the edges of
UC1602I internal clock. To ensure consistent
system states, wait at least 10uS after System
Reset or Set Display Enable command.
E
UC1602I contains internal logic to check whether
V
column drivers from their OFF states. When
exiting Sleep Mode and Reset Mode, column and
row drivers will not be activated until UC1602I
internal voltage sources are restored to their
proper values.
P
UC1602I power-up sequence is simplified by
built-in “Power Ready” flags and by the automatic
invocation of System-Reset command after
Power-ON-Reset . System programmer are only
required to wait 4~6 ms before starting to issue
commands to UC106. No additional commands
or waits are required between enabling of the
charge pump, turning on the display drivers,
writing to RAM or any other commands.
P
To prevent the charge stored in capacitors C
C
is switched off, use Reset mode to enable the
built-in charge draining circuit to discharge these
external capacitors.
UC1602I draining resistance is 1K for both V
and V
Set Display Enable , and System Reset .
HANGING
XITING
LCD
OWER
OWER
B–
Set Display Enable “OFF”
Set Display Enable “ON”
, and C
and V
RST_ pin pulled “L”
B+
Reset command
-U
-D
Power ON reset
. It is recommended to wait 3 x RC for
P
P
OWN
OWER
O
LCD
D
S
Action
PERATION
B0
EQUENCE
is ready before releasing row and
Table 12: OM changes
S
, C
from damaging the LCD when V
S
EQUENCE
AVE
B1
and C
M
M
ODES
ODE
LCD
. To drain these
Product Specifications
Normal
Mode
Sleep
Reset
OM
11
10
00
©2000
B+
LCD
,
DD