wm8400 Wolfson Microelectronics plc, wm8400 Datasheet - Page 71

• Manufacturer Part Number: wm8400
• Description: Wolfson Audioplustm Hi-fi Audio Codec And Power Management Unit For Mobile Multimedia
• Manufacturer: Wolfson Microelectronics plc

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Pre-Production
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8400 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full
scale input level is proportional to AVDD. See “Electrical Characteristics” for further details. Any input
signal greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits.
Table 32 ADC Enable Control
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for
a given eight-bit code X is given by:
0.375 × (X-192) dB for 1 ≤ X ≤ 239;
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the
ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to ADC_VU. This makes it possible to update the gain of both channels simultaneously.
Table 33 ADC Digital Volume Control
R3 (03h)
R16 (10h)
R17 (11h)
REGISTER
ADDRESS
REGISTER
ADDRESS
8
7:0
8
7:0
BIT
1
0
BIT
ADC_VU
ADCL_VOL
[7:0]
ADC_VU
ADCR_VOL
[7:0]
ADCL_ENA
(rw)
ADCR_ENA
(rw)
LABEL
LABEL
MUTE for X = 0
N/A
1100_0000b
(0dB)
N/A
1100_0000b
(0dB)
0b
0b
DEFAULT
DEFAULT
Left ADC Enable
0 = ADC disabled
1 = ADC enabled
Right ADC Enable
0 = ADC disabled
1 = ADC enabled
+17.625dB for 239 ≤ X ≤ 255
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be updated
simultaneously
Left ADC Digital Volume
(See Table 34 for volume range)
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be updated
simultaneously
Right ADC Digital Volume
(See Table 34 for volume range)
DESCRIPTION
DESCRIPTION
PP, April 2009, Rev 3.0
WM8400
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