atr2434 ATMEL Corporation, atr2434 Datasheet - Page 16

• Manufacturer Part Number: atr2434
• Description: Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
• Manufacturer: ATMEL Corporation

Table 11. Receive Interrupt Status
Note:
16
Bit
7
6
5
4
3
2
Valid B
Name
Valid B
Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the
EOF B
Full B
Valid A
Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the
7
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be imple-
mented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example,
the receive status will read 0 if the IC is not in receive mode. These register are read-only.
Addr: 0x08
ATR2434 [Preliminary]
Flow Violation B
Description
The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.
1 = All bits are valid for Receive SERDES Data B
0 = Not all bits are valid for Receive SERDES Data B
When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
Receive SERDES Data B register (Reg 0x0B).
1 = Overflow/underflow interrupt pending for Receive SERDES Data B
0 = No overflow/underflow interrupt pending for Receive SERDES Data B
Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B)
before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data
B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status
register (Reg 0x08)
The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.
1 = EOF interrupt pending for Channel B
0 = No EOF interrupt pending for Channel B
An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is
cleared by reading the Receive Interrupt Status register (Reg 0x08)
The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.
1 = Receive SERDES Data B full interrupt pending
0 = No Receive SERDES Data B full interrupt pending
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data
B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.
1 = All bits are valid for Receive SERDES Data A
0 = Not all bits are valid for Receive SERDES Data A
When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
Receive SERDES Data A register (Reg 0x09).
1 = Overflow/underflow interrupt pending for Receive SERDES Data A
0 = No overflow/underflow interrupt pending for Receive SERDES Data A
Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09)
before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data
A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status
register (Reg 0x08)
6
EOF B
5
Full B
REG_RX_INT_STAT
4
Valid A
3
Flow Violation A
2
EOF A
1
Default: 0x00
4822C–ISM–09/04
Full A
0