atr2434 ATMEL Corporation, atr2434 Datasheet - Page 9

• Manufacturer Part Number: atr2434
• Description: Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
• Manufacturer: ATMEL Corporation

Interrupts
Wake Interrupt
Transmit Interrupts
Receive Interrupts
4822C–ISM–09/04
The ATR2434 features three sets of interrupts: transmit, receive, and a wake interrupt.
These interrupts all share a single pin (IRQ), but can be independently enabled/
disabled. In transmit mode, all receive interrupts are automatically disabled, and in
transmit mode all receive interrupts are automatically disabled. However, the contents of
the enable registers are preserved when switching between transmit and receive
modes.
Interrupts are enabled and the status reads through 6 registers: Receive Interrupt
Enable (Reg 0x07), Receive Interrupt Status (Reg 0x08), Transmit Interrupt Enable
(Reg 0x0D), Transmit Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary to read the relevant inter-
rupt status register to determine which event caused the IRQ pin to assert. Even when a
given interrupt source is disabled, the status of the condition that would otherwise cause
an interrupt can be determined by reading the appropriate interrupt status register. It is
therefore possible to use the devices without making use of the IRQ pin at all. Firmware
can poll the interrupt status register(s) to wait for an event, rather than using the IRQ
pin.
The polarity of all interrupts can be set by writing to the Configuration register
(Reg 0x05), and it is possible to configure the IRQ pin to be open drain (if active low) or
open source (if active high).
When the PD pin is low, the oscillator is stopped. After PD is deasserted, the oscillator
takes time to start, and until it has done so, it is not safe to use the SPI interface. The
wake interrupt indicates that the oscillator has started, and that the device is ready to
receive SPI transfers.
The wake interrupt is enabled by setting bit 0 of the Wake Enable register (Reg 0x1C,
bit 0 = 1). Whether or not a wake interrupt is pending is indicated by the state of bit 0 of
the Wake Status register (Reg 0x1D, bit 0). Reading the Wake Status register
(Reg 0x1D) clears the interrupt.
Four interrupts are provided to flag the occurrence of transmit events. The interrupts are
enabled by writing to the Transmit Interrupt Enable register (Reg 0x0D), and their status
may be determined by reading the Transmit Interrupt Status register (Reg 0x0E). If more
than 1 interrupt is enabled, it is necessary to read the Transmit Interrupt Status register
(Reg 0x0E) to determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in detail in the section
“Register Descriptions” on page 10.
Eight interrupts are provided to flag the occurrence of receive events, four each for
SERDES A and B. In 64 chips/bit and 32 chips/bit DDR modes, only the SERDES A
interrupts are available, and the SERDES B interrupts will never trigger, even if enabled.
The interrupts are enabled by writing to the Receive Interrupt Enable register
(Reg 0x07), and their status may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is necessary to read the
Receive Interrupt Status register (Reg 0x08) to determine which event caused the IRQ
pin to assert.
The function and operation of these interrupts are described in detail in the section
“Register Descriptions” on page 10.
ATR2434 [Preliminary]
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