ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 169

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt04.01
August 14, 2000
22-20
Bit(s)
25
24
23
Hold Mode
Queue on DMA Complete
Inhibit Status Update when DMA
Complete
Destination Address Specifier
Function
When set, bits 31-28 are redefined to allow the source or destination address to be
held instead of incremented. Bit 29 becomes hold destination address and bit 28
becomes hold source address. This allows a single DMA descriptor to do an N-to-1 or
1-to-N transfer. For example, an entire scatter DMA list can be freed to a receive
queue enqueue register. The address being held must be a register address. When
holding, the maximum length is 252 bytes. When holding, the source or destination is
incremented by four when the DMA completes (for auto-increment mode). Bit 31
becomes destination address 64 bits wide. Bit 30 becomes source address 64 bits
wide. This destination is required to properly update 64 bit wide registers when hold
mode is asserted.
When this bit is set, the upper 26 bits of the DMAQS System Descriptor Address regis-
ter will be queued to the DMA event queue when the DMA completes. If descriptors are
not being used to set up the DMA, then before starting the DMA, the DMAQS System
Descriptor Address register should be loaded before starting the DMA with a value to
identify this transfer. If descriptors are being used, the DMAQS System Descriptor
Address register will be loaded automatically with the system address of the descriptor
block at the time it is processed.
Normally a bit will be set in the status register when the DMA completes without error.
If this bit is set, this update will not be done. This bit is useful when multiple DMAs are
to be done and an interrupt is only desired on the last transfer. The DMA error status
bits are not affected by this bit.
These bits specify how the destination address should be used for this DMA descriptor.
The following are the valid patterns:
000
001
010
011
100
101
110
111
Others Reserved: Reserved and flagged as errors.
IBM3206K0424 memory address: The destination address specifies an
IBM3206K0424 internal memory address.
PCI Bus Address: The destination address specifies a PCI bus address.
IBM3206K0424 Register Address: The destination address specifies an
IBM3206K0424 register address. Only the low 16 bits must be specified.
Get IBM3206K0424 Buffer: The low four bits of the destination address specify
a pool ID from which to get a buffer. If a buffer is not available, a zero destina-
tion address event or appropriate status is raised. Otherwise the buffer
address is used as an IBM3206K0424 memory address.
Auto Increment Destination Address: The destination address is sourced from
the previous DMA instead of the destination address specified in the
descriptor.
Next Source Address: The destination address is the address of the source
address field of the next descriptor in the current DMA chain. Using this feature
allows indirection.
Next Destination Address: The destination address is the address of the desti-
nation address field of the next descriptor in the current DMA chain. Using this
feature allows operations like doing a get buffer in the DMA descriptor chain.
Offset Destination Address: The Destination Address is a positive offset from
the DMAQS Buffer Address Register. Using this feature allows, for example,
storing the checksum value in the header of the packet.
Description
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 169 of 676
IBM3206K0424