ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 234

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
7.20: ARBIT Packet Config Register
The bits in this register control the operation of the Packet Memory arbiter.
Length
Type
Address
Power On Value
Restrictions
ATM Packet/Control Memory Arbitration Logic (ARBIT)
Page 234 of 676
3
Bit(s)
3-2
1
0
2
1
Reserved
This bit controls the arbit entity state debug mux. When set, the incoming entity requests and outgoing acknowledges are
routed to the entity state pins. When reset, the internal state information is routed to the entity state pins.
When set, this bit forces all operations to Packet Memory to be serialized. An operation from one entity must be entirely com-
plete before an operation from another entity will be started. When reset, if the memory operation in process can be over-
lapped, a second operation will be started before the first operation is complete.
0
4 bits
Clear/Set
XXXX 0EB8 and BC
X’0’
None
Description
pnr25.chapt04.01
August 14, 2000
Preliminary