ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 473

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
17.11: PCORE JTAG Debug Control Register
The PCORE JTAG Debug Control Register enables the JTAG port or a PCI interface processor debugger to
control the processor core.
Length
Type
Address
Power on Reset value
Restrictions
pnr25.chapt05.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
28-27
Bit(s)
24-0
31
30
29
26
25
Control
Stop Processor
Block Folding
Single Step
Reset Control
Unconditional Debug Event
Freeze Timers while Stopped
Reserved
Reset
Name
32 bits
Read/Write
XXXX 4200
X’00 00 00 00’
None
The processor normally dispatches two instructions at a time. Setting this bit forces
instruction dispatches to be serialized.
Setting this bit when the processor is stopped causes the processor to execute one or
two instructions depending on the value of bit 30. This bit automatically clears itself
after one cycle.
These bits potentially generate one of three resets depending on their value. They
automatically reset to B’00’ after one cycle. The bits decode as follows:
’00’
’01’
’10’
’11’
This bit generates an interrupt to the processor. It automatically resets to B’0’ after one
cycle.
This bit freezes the state of all timers in the core if the processor is stopped.
Reserved.
This bit forces the processor to halt execution.
No reset
Core reset
Chip reset
System reset
Reserved
Description
IBM Processor for Network Resources
8
7
6
Processor Core (PCORE)
5
4
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