ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 32

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Queues
The IBM Processor for Network Resources makes extensive use of cached single memory operation atomic
queues:
Note: In order to maintain the atomicity of 64-bit atomic transfers, the user must ensure that 64-bit transfers
are bus atomic within the particular bus system in which the IBM3206K0424 is being used.
Scheduling
There is extensive support for transmit scheduling. Please see Transmit Path on page 37 and Transmit
Scheduling Capabilities on page 38 for details.
Internal Architecture
Page 32 of 676
Transmit queues
Receive queues
Event queues
The interface to the scheduling entity. Blocks and Frames can be queued to Logical Channels.
Based on the settings in the Logical Channel Descriptor (receive side). Cells arriving can be queued indi-
vidually, collected into frames, or stored in FIFO buffers.
When a frame is transmitted, its memory can be “garbage collected” or a reference to the frame can be
placed on an event queue for software to handle.
If either a FIFO buffer scheme or frame buffer scheme is used to source or sink data on a logical channel,
it is possible to set thresholds on the buffering that will cause events to be queued. When a threshold is
crossed (for instance if a transmitting LC is about to run out of data to transmit), an event will be queued.
Software can read these events either by polling or by being interrupted and can schedule tasks to pro-
vide more data.
Events can be scheduled on the reception of the first N bytes of a frame so that header processing can
begin even before the complete frame is received. This will allow “cut-through” routing to be supported.
pnr25.chapt01.01
August 14, 2000
Preliminary