am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 121

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

7–0 SWSTYLE
1-988
SWSTYLE
All other
combs.
[7:0]
00h
01h
02h
AMD
LANCE/
PCnet-
PCnet-
ILACC
Name PCNET SSIZE32 Interpretations
Style
Res.
ISA
PCI
Table 12. SWSTYLE Values
Undef.
CSR-
1
0
1
Software Style register. The
value in this register determines
the style of I/O resources that
shall be used by the PCnet-PCI
controller. The Software Style
selection will affect the interpre-
tation of a few bits within the CSR
space and the width of the de-
scriptors and initialization block.
Specifically:
Undef.
0
1
1
Altered Bit
ALL CSR4 bits will
function as defined in
the CSR4 section.
TMD1[29] functions as
ADD_FCS
CSR4[9:8], CSR4[5:4]
and CSR4[1:0] will
have no function, but
will be writeable and
readable.
CSR4[15:10], CSR4[7:6]
and CSR4[3:2] will
function as defined in the
CSR4 section.
TMD1[29] becomes
NO_FCS.
ALL CSR4 bits will
function as defined in
the CSR4 section.
TMD1[29] functions as
ADD_FCS
Undef.
P R E L I M I N A R Y
Am79C970
BCR21: Interrupt Control
Bit
31–16 RES
15–0 INTCON
Name
All PCnet-PCI controller CSR
bits and BCR bits and all descrip-
tor, buffer and initialization block
entries not cited in the table
above are unaffected by the Soft-
ware Style selection and are
therefore always fully functional
as specified in the CSR and BCR
sections.
Read/write accessible only when
STOP bit is set.
The SWSTLYE register will con-
tain the value 00h following
H_RESET or S_RESET and will
be unaffected by STOP.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Writes to
this register will have no effect on
the operation of the PCnet-PCI
controller.