am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 89

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

11
10
9
8
7–6
5
1-956
AMD
LAPPEN
MERRM
IDONM
RINTM
TINTM
RES
or S_RESET and is not affected
by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and unable to set
INTR flag in CSR0.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Receive
RINTM is set, the RINT bit in
CSR0 will be masked and unable
to set INTR flag in CSR0.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Transmit
TINTM is set, the TINT bit in
CSR0 will be masked and unable
to set INTR flag in CSR0.
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Initialization
IDONM is set, the IDON bit in
CSR0 will be masked and unable
to set INTR flag in CSR0.
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved locations. Read and
written as ZEROs.
Look-Ahead Packet Processing
Enable. When set to a ONE, the
LAPPEN bit will cause the
PCnet-PCI controller to generate
an interrupt following the descrip-
tor write operation to the first
buffer of a receive packet. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a ONE also
enables the PCnet-PCI controller
to read the STP bit of receive de-
scriptors. PCnet-PCI controller
will use the STP information to
determine where it should begin
writing a receive packets data.
Note that while in this mode, the
PCnet-PCI controller can write
intermediate packet data to
Interrupt
Interrupt
Done
Mask.
Mask.
Mask.
P R E L I M I N A R Y
Am79C970
If
If
If
buffers whose descriptors do not
contain STP bits set to ONE. Fol-
lowing the write to the last de-
scriptor used by a packet, the
PCnet-PCI controller will scan
through the next descriptor en-
tries to locate the next STP bit
that is set to a ONE. The PCnet-
PCI controller will begin writing
the next packets data to the
buffer pointed to by that descrip-
tor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = ONE, then some descrip-
tors/buffers may be skipped in
the ring. While performing the
search for the next STP bit that is
set to ONE, the PCnet-PCI con-
troller will advance through the
receive descriptor ring regard-
less of the state of ownership
bits. If any of the entries that are
examined during this search indi-
cate PCnet-PCI controller own-
ership of the descriptor but also
indicate STP = 0, then the
PCnet-PCI controller will reset
the OWN bit to ZERO in these
entries. If a scanned entry indi-
cates host ownership with STP =
0, then the PCnet-PCI controller
will not alter the entry, but will ad-
vance to the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the PCnet-PCI controller, then
the PCnet-PCI controller will stop
advancing through the ring en-
tries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the PCnet-PCI control-
ler, then the PCnet-PCI controller
will stop advancing through the
ring entries, store the descriptor
information that it has just read,
and wait for the next receive to
arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“header” portion of a receive
packet will always be written to a
particular memory area, and the
“data” portion of a receive packet