am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 61

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Power Savings Modes
The PCnet-PCI controller supports two hardware power
savings modes. Both are entered by driving the SLEEP
pin LOW.
The PCI interface section is not effected by SLEEP. In
particular, access to the PCI configuration space re-
mains possible. None of the configuration registers will
be reset by SLEEP. All I/O accesses to the PCnet-PCI
controller will result in a PCI target abort response.
The first power saving mode is called coma mode. In
coma mode, the PCnet-PCI controller has no means to
use the network to automatically wake itself up. Coma
mode is enabled when the AWAKE bit in BCR2 is reset.
Coma mode is the default power down mode.
The second power saving mode is called snooze mode.
In snooze mode, enabled by setting the AWAKE bit in
BCR2 and driving the SLEEP pin LOW, the T-MAU re-
ceive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LNKST output is the only
one of the LED pins that continues to function. The
LNKSTE bit must be set in BCR4 to enable indication of
a good 10BASE-T link if there are link beat pulses or
valid frames present. This LNKST pin can be used to
drive an LED and/or external hardware that directly con-
trols the SLEEP pin of the PCnet-PCI controller. This
configuration effectively wakes the system when there
is any activity on the 10BASE-T link. Snooze mode can
be used only if the T-MAU is the selected network port.
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AMD
P R E L I M I N A R Y
Am79C970
Link beat pulses are not transmitted during snooze
mode.
If the REQ output is active when the SLEEP pin is as-
serted, then the PCnet-PCI controller will wait until the
GNT input is asserted. Next, the PCnet-PCI controller
will deassert the REQ pin and finally, it will internally en-
ter either the coma or snooze sleep mode.
Before the sleep mode is invoked, the PCnet-PCI con-
troller will perform an internal S_RESET. This
S_RESET operation will not affect the values of the BCR
registers or the PCI configuration space.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the asser-
tion of SLEEP until three CLK cycles after the comple-
tion of a valid pin RST operation.
Software Access
Configuration Registers
The PCnet-PCI controller supports the 64-byte header
portion of the configuration space as predefined by the
PCI specification revision 2.0. None of the device spe-
cific registers in locations 64 – 255 are used. The layout
of the configuration registers in the header region is
shown in the table below. All registers required to iden-
tify the PCnet-PCI controller and its function are imple-
mented. Additional registers are used to setup the
configuration of the PCnet-PCI controller in a system.