am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 91

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

14
13
12
11 APAD_XMT
1-958
AMD
DMAPLUS
DPOLL
TIMER
the Runt Packet Accept (RPA) bit
(CSR124, bit 3) may be changed
only when ENTST is set to ONE.
To enable RPA, the user must
first write a ONE to the ENTST
bit. Next, the user must first write
a ONE to the RPA bit (CSR124,
bit 3). Finally, the user must write
a ZERO to the ENTST bit to take
the device out of test mode op-
eration. Once, the RPA bit has
been set to ONE, the device will
remain in the Runt Packet Accept
mode until the RPA bit is cleared
to ZERO.
Read/Write accessible. ENTST
is cleared by H_RESET or
S_RESET and is unaffected by
the STOP bit.
When DMAPLUS = “1”, DMA
Burst Counter in CSR80 is dis-
abled. If DMAPLUS = “0”, the
counter is enabled.
Read/Write
DMAPLUS is cleared by H_RE-
SET or S_RESET and is unaf-
fected by the STOP bit.
Timer Enable Register. If TIMER
is set, the Bus Timer Register,
CSR82 is enabled. If TIMER is
cleared, the Bus Timer Register
is disabled.
Read/Write accessible. TIMER is
cleared
S_RESET and is unaffected by
the STOP bit.
Disable
DPOLL is set, the Buffer Man-
agement Unit will disable trans-
mit polling. Likewise, if DPOLL is
cleared, automatic transmit poll-
ing is enabled. If DPOLL is set,
TDMD bit in CSR0 must be set in
order to initiate a manual poll of a
transmit descriptor. Transmit de-
scriptor polling will not take place
if TXON is reset.
Read/Write accessible. DPOLL
is cleared by H_RESET or
S_RESET and is unaffected by
the STOP bit.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
tire frame including pad, and ap-
pended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit.
Transmit
by
H_RESET
accessible.
Polling.
P R E L I M I N A R Y
Am79C970
or
If
10 ASTRP_RCV
9
8
7
6
5
RCVCCO
MFCOM
MFCO
RES
RES
Read/Write
APAD_XMT
H_RESET or S_RESET and is
unaffected by the STOP bit.
Auto Strip Receive. When set,
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write
ASTRP_RCV
H_RESET or S_RESET and is
unaffected by the STOP bit.
Missed Frame Counter Overflow
Interrupt.
Indicates the MFC (CSR112)
wrapped around. Can be cleared
by writing a 1 to this bit. Also
cleared by H_RESET, S_RESET
or by asserting the STOP bit.
Writing a 0 has no effect.
When MFCO is set, INTA is as-
serted if IENA is ONE and the
mask bit MFCOM is ZERO.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will
never set the value of this bit to
ONE.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will be
unable to set INTR in CSR0.
Set to a ONE by H_RESET or
S_RESET, unaffected by the
STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI controller will set
the value of this bit to ZERO.
Reserved location. Written as
ZERO and read as ZERO.
Reserved location. This bit may
be written to as either a ONE or a
ZERO, but will always be read as
a ZERO. This bit has no effect on
PCnet-PCI controller operation.
Receive
Overflow.
Indicates the Receive Collision
Counter
around. Can be cleared by
(CSR114)
Collision
is
is
cleared
cleared
accessible.
accessible.
wrapped
Counter
by
by