s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 58

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

58
RY/BY#: Ready/Busy#
DQ6: Toggle Bit I
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.
Table 14
T oggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. T oggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
any sector address within the sector being erased. During chip erase, a valid address is
any non-protected sector address.
with DQ5.
shows the outputs for RY/ BY#.
Figure 6. Data# Polling Algorithm
CC
No
.
A d v a n c e
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
S29PL129J for MCP
DQ5 = 1?
START
FAIL
No
Yes
No
Yes
Yes
I n f o r m a t i o n
PASS
S29PL129J_MCP_00_A0 June 4, 2004