am42dl1614dt70it Meet Spansion Inc., am42dl1614dt70it Datasheet - Page 56

• Manufacturer Part Number: am42dl1614dt70it
• Description: 16 Mbit X8/x16 Flash And 4 Mbit X16 Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
6. Output data may be present on the bus at this time; input signals should not be applied.
7. If OE# is high during the write cycle, the outputs will remain at high impedance.
January 9, 2002
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
Figure 31. SRAM Write Cycle—CE1#s Control
WP
(See Note 6)
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
P R E L I M I N A R Y
t
AS
(See Note 2)
Am42DL16x4D
(See Note 3)
WR
applied in case a write ends as CE1#s or WE# going high.
t
t
AW
CW
t
(See Note 5)
WC
t
BW
t
WP
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
(See Note 4)
High-Z
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