w86l388d Winbond Electronics Corp America, w86l388d Datasheet
w86l388d
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w86l388d Summary of contents
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... W86L388D Winbond Host Interface SD/MMC Memory Card Bridge ...
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... W86L388D Data Sheet Revision History Pages Dates 1 08/2001 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury ...
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... ELECTRICAL CHARACTERISTICS .........................................................................................................15 8 ...................................................................................................................................15 AXIMUM ATINGS 8 ECOMMENDED PERATING 8 OWER UPPLY HARACTERISTICS 8. IGITAL HARACTERISTICS 8. ..........................................................................................................................16 IMING HARACTERISTICS 9. HOW TO READ THE TOP MARKING ......................................................................................................22 10.PACKAGE DIMENSIONS ...........................................................................................................................23 11. REFERENCE SCHEMATIC .......................................................................................................................24 Table of Content ................................................................................................................13 C ....................................................................................................15 ONDITIONS ..............................................................................................................15 ........................................................................................................................ W86L388D Preliminary Publication Release Date: August 2001 Revision 0.50 ...
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... GENERAL DESCRIPTION The W86L388D is a SD/MMC host interface bridge used between host microprocessor and SD/MMC. The data width of host microprocessor can be 8-bit or 16-bit. W86L388D can support synchronous or asynchronous type of host interface. It also supports DMA or Interrupt type of transfer mode to improve data transfer performance between host microprocessor and SD/MMC. W86L388D is fit for most of IA devices, such as PDA, Cellular Phone, DSC, and MP3 player ...
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... D15/A0 41 D14 42 VSS 43 VDD D13 44 D12 45 46 D11 47 D10 W86L388D Preliminary GIO3 23 GIO4 22 SD6 21 SD5 20 SD4 19 VDD 18 VSS 17 SD3 16 SD2 15 SD1 14 XTO 13 XTI 11 12 Publication Release Date: August 2001 Revision 0.50 ...
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... High byte (D15 to D8) write control pin, active low. Type 2: High byte (D15 to D8) data valid pin, active low. Type 1: Low byte (D7 to D0) write control pin, active low. Type 2: Low byte (D7 to D0) data valid pin, active low W86L388D Preliminary Description Publication Release Date: August 2001 Revision 0.50 ...
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... Host interface type 2 select pin type 1 mode type 2 mode. 5-bit general input output port signals. GIO0 pin can be used as dedicate card detecttion. Reset input, hardware reset input, active low. Power supply 3.3V Ground - 4 - W86L388D Preliminary Description Publication Release Date: August 2001 Revision 0.50 ...
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... Register File /Write 17 Byte Rsp Reg Serial to Parallel 6 Byte CMD Reg Parallel to Serial 8 Byte FIFO Serial to Parallel 8 Byte FIFO Parallel to Serial Interrupt Circuit Fig. 5-1 Block Diagram of W86L388 - 5 - W86L388D Preliminary VDD VSS General Port Registers SD Access Circuit Command or Response Data Packing or Circuit ...
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... GIO data GIO interrupt status Index data register W86L388D Preliminary Control ...
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... Nac time out register Status W86L388D Preliminary Setting register Data length ...
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... The Host interface type 1 is selected when XTYP2 pin is low. Figure 7-1 shows the timing of CPU read and write in type 1. Figure 7-2 is the timing of CPU write high byte and write low byte. A[3:1] D[15:0] XCSN XRDN XWRHN XWRLN Fig. 7-1 16-bit Read and Write Access in Host I/F Type 1. DO[15:0] Publication Release Date: August 2001 - 8 - W86L388D Preliminary DI[15:0] Revision 0.50 ...
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... The Host interface type 2 is selected when XTYP2 pin is high. Figure 7-3 shows the timing of CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-4 shows the timing of CPU read write in type 2 and the access cycle is 2-cycle access. DI[15:8] DI[7:0] Publication Release Date: August 2001 - 9 - W86L388D Preliminary Revision 0.50 ...
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... Read cycle XBE[1:0] Fig. 7-3 Read and Write Timing in Host I/F Type 2, 3-Cycle Access. HCKI A[3:1] DO[15:0] D[15:0] XCSN XASN XRDYN XRWN Read cycle XBE[1:0] Fig. 7-4 Read and Write Timing in Host I/F Type 2, 2-Cycle Access. W86L388D DI[15:0] Write cycle DI[15:0] Write cycle Publication Release Date: August 2001 - 10 - Preliminary Revision 0.50 ...
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... XDRQN will hold at active state until the data has been transferred completedly. Figure 7-6 is the waveform of DMA access transmit data buffer in DAKN = high. System Clock A[3:1] D[15:0] XCSN XRDN XDRQN XDAKN Fig. 7-5 DMA Access Receive Data Buffer (DAKEN = low). 010 - 11 - W86L388D Preliminary 010 Publication Release Date: August 2001 Revision 0.50 ...
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... XINTN pin will return to high when read the interrupt register and if the interrupt source is not existed. Figure 7-7 is the timing of interrupt. System_ Clock A[3:1] D[15:0] XCSN XRDN XINTN 010 011 Fig. 7-7 Timing of Interrupt in W86L388D Preliminary 010 Publication Release Date: August 2001 Revision 0.50 ...
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... Data buffer reset is used to reset the receive data buffer and transmit data buffer simutaneously, the serial interface command will affected if the data receive or transmit command is progressing. Internal logic state and the content of registers are not affected. W86L388D Publication Release Date: August 2001 - 13 - Preliminary Revision 0 ...
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... Clock Source The clock source of W86L388 is the waveform of XTO pin, if crystal is connected, the frequency may be from 3.58MHz to 25MHz, if the clock source is from external clock, XTI may be used as clock input and the maximum frequency is 25MHz. W86L388D Publication Release Date: August 2001 - 14 - Preliminary ...
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... Condition Symbol Power Supply 3.3V) I VDD VDD I VDD = 3.3V and temperature = 25 : and are for design aid only, not configured as power down mode, output without VDD VSS - 15 - W86L388D Preliminary Rating -0 VDD -65 to 150 Rating V 3.0 to 3.6 VDD V 2.7to 3.0 VDD ...
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... Symbol Min fXTI 1 tXTI 10 wh tXTI 10 wl tXTI - r tXTI - f tXTO - d fXTI 3.58 fHCLK 1 tHCLK 10 wh tHCLK 10 wl tHCLK - I tHCLK - W86L388D Preliminary Min Max Units ‡ Typ 0.9 VDD 0.1 VDD 0.9 VDD 0.1 VDD 0.7 VDD 0.3 VDD Typ Max Units Notes - 20 MHz - - ...
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... TINT Publication Release Date: August 2001 - 17 - W86L388D Preliminary Units Notes cycle 5 Revision 0.50 ...
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... Fig. 8-1 Timing Characteristic of XTI, XTO and HCKI. Symbol Min tSD3 5 d tSD3D 10 su tSD3 tSDn d tSDn 10 su tSDn 5 h tXTI tXTI wh tXTO d tXTI f tHCKI tHCKI wh tHCKI tHCKI W86L388D Preliminary Typ Max Units - tXTI r wl Publication Release Date: August 2001 Revision 0.50 Notes 2 2 ...
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... XTO tDRQ XDRQN XDAKN (Note 1) Fig. 8-3 DMA Timing Characteristic. Note 1: May be XRDN or XWRHN or XWRLN signals when XDAKEN = low. XTO tINT d XINTN XRDN Fig. 8-4 Interrupt Timing Characteristic acc d Publication Release Date: August 2001 - 19 - W86L388D Preliminary DI[15: tDRQ h tINT h Revision 0.50 ...
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... DI DO Fig. 8-5 Host Interface Type 2 Timing Characteristic. SD4 tSD3 SD3 (output) SD3 (input) Fig. 8-6 Serial Interface SD3 Timing Characteristic (SD Mode). tIF2 tRDY d tRDY tSD3 d d tSD3 h tSD3 su Publication Release Date: August 2001 - 20 - W86L388D Preliminary h tA2 Revision 0.50 ...
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... Fig. 8-8 Serial Interface SD3 Timing Characteristic (MMC Mode). SD4 tSDn d SDn (output) SDn (input) Fig. 8-9 Serial Interface SDn Timing Characteristic (MMC Mode). SDn: SD1, SD2, SD5, SD6 tSDn d tSDn tSDn su h tSD3 d tSD3 h tSD3 tSD3 su tSDn d tSDn tSDn su h Publication Release Date: August 2001 - 21 - W86L388D Preliminary su Revision 0.50 ...
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... S MART@ W86L388D 118GA01ASB 1st line: Winbond logo and SMART@IO Mark 2nd line: Part number of W86L388D 3rd line: Tracking code 118: packages made in '01, week 18 G: assembly house ID; A means ASE, O means OSE, G means revision; A means version A, B means version B 01A: for internal use ...
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... D 6.90 7.00 0.272 0.276 0.280 7.10 E 7.00 0.272 0.276 0.280 6.90 7.10 e 0.014 0.020 0.35 0.50 0.65 0.026 H 0.350 0.358 8.90 9.00 9.10 0.354 D H 0.350 0.354 0.358 8.90 9.00 9. 0.030 0.018 0.024 0.45 0.60 0.75 L 0.039 1. 0.004 0. Publication Release Date: August 2001 - 23 - W86L388D Preliminary 6 Revision 0.50 ...
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... SD1 Case SD/MMC Card Scoket D To Intel StrongARM interface (16 bit) VCC33 C8 C9 C10 C11 + + + + 0.1u 0.1u 0.1u 0.1u D inbond WINBOND ELECTRONICS CORP_ Size Document Number W86L388D Reference Schematic (for StrongARM) Date: Tuesday, October 02, 2001 Sheet 1 of Publication Release Date: August 2001 Revision 0.50 Rev 2.2 1 ...
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... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Publication Release Date: August 2001 - 25 - W86L388D Preliminary Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 ...