mt9v011ia9stces aptina, mt9v011ia9stces Datasheet - Page 12

• Manufacturer Part Number: mt9v011ia9stces
• Description: Mt9v011 1/4-inch Vga Digital Image Sensor
• Manufacturer: aptina

Serial Bus Description
Protocol
Sequence
Bus Idle State
PDF:0560901182/Source 6061803135
MT9V011_IBGA_DS - Rev. C 6/10 EN
Registers are written to and read from the MT9V011 through the two-wire serial inter-
face bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK),
which is driven by the serial interface master. Data is transferred into and out through
the MT9V011 serial data (S
1.5KΩ resistor. Either the slave or master device can pull the SDATA line down—the
serial interface protocol determines which device is allowed to pull the S
at any given time. The registers are 16 bits wide, and can be accessed through 16- or 8-bit
two-wire serial bus sequences.
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device 8-bit address
• a(n) (no) acknowledge bit
• an 8-bit message
• a stop bit
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device’s 8-bit address. The last bit of the address deter-
mines if the request will be a read or a write, where a “0” indicates a write and a “1” indi-
cates a read. The slave device acknowledges its address by sending an acknowledge bit
back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight bits. The MT9V011 uses 16-bit data
for its internal registers, thus requiring two 8-bit transfers to write to one register. After
16 bits are transferred, the register address is automatically incremented, so that the next
16 bits are written to the next register address. The master stops writing by sending a
start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data eight bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit. The MT9V011
allows for 8-bit data transfers through the two-wire serial interface by writing (or
reading) the most significant eight bits to the register and then writing (or reading) the
least significant eight bits to Reg0x80 (128).
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
DATA
12
) line. The S
MT9V011 1/4-INCH VGA DIGITAL IMAGE SENSOR
DATA
line is pulled up to V
Aptina eserves the right to change products or specifications without notice.
©2009 Aptina Imaging Corporation All rights reserved.
DD
off-chip by a
DATA
Preliminary
line down