mt9v011ia9stces aptina, mt9v011ia9stces Datasheet - Page 23

• Manufacturer Part Number: mt9v011ia9stces
• Description: Mt9v011 1/4-inch Vga Digital Image Sensor
• Manufacturer: aptina

Propagation Delays for PIXCLK and Data Out Signals
Propagation Delays for FRAME_VALID and LINE_VALID Signals
Figure 19:
Figure 20:
PDF:0560901182/Source 6061803135
MT9V011_IBGA_DS - Rev. C 6/10 EN
Propagation Delays for PIXCLK and Data Out Signals
Propagation Delays for FRAME_VALID and LINE_VALID Signals
PIXCLK
CLKIN
FRAME_VALID
The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data
outputs change on the falling edge of the master clock, with the pixel clock rising on the
subsequent rising edge of the master clock.
The LINE_VALID and FRAME_VALID signals change on the same falling master clock
edge as the data output. The LINE_VALID goes HIGH on the same falling master clock
edge as the output of the first valid pixel's data and returns LOW on the same master
clock falling edge as the end of the output of the last valid pixel's data.
As shown in the “Output Data Timing” on page 10, FRAME_VALID goes HIGH 6 pixel
clocks prior to the time that the first LINE_VALID goes HIGH. It returns LOW at a time
corresponding to 6 pixel clocks after the last LINE_VALID goes LOW.
LINE_VALID
D
OUT
CLKIN
(9:0)
t PLH
D
P
OUT
t PLH
(9:0)
F,L
t R
t PLH
D
t F
OUT
D
,
23
t PHL
(9:0)
D
FRAME_VALID
LINE_VALID
MT9V011 1/4-INCH VGA DIGITAL IMAGE SENSOR
CLKIN
D
OUT
(9:0)
t PHL
t PHL
Aptina reserves the right to change products or specifications without notice.
D
t OH
OUT
P
F,L
(9:0)
©2009 Aptina Imaging Corporation. All rights reserved.
Preliminary