mt9v011ia9stces aptina, mt9v011ia9stces Datasheet - Page 17

• Manufacturer Part Number: mt9v011ia9stces
• Description: Mt9v011 1/4-inch Vga Digital Image Sensor
• Manufacturer: aptina

Pixel Clock Speed
Reset
Digital Zoom
PDF:0560901182/Source 6061803135
MT9V011_IBGA_DS - Rev. C 6/10 EN
If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will
be extended by (K x Reg0x0C - (row time - 444)) clock cycles.
Where :
K = 4 when Reg0x07[4] = 0, and
K = 2 when Reg0x07[4] = 1
In this expression the row time term corresponds to the number of rows integrated. The
overhead time is the time between the READ cycle and the RESET cycle, and the final
term is the effect of the reset delay.
Typically, the value of Reg0x09 (Shutter Width) is limited to the number of rows per
frame (which includes vertical blanking rows), such that the frame rate is not affected by
the integration time. If Reg0x09 is increased beyond the total number of rows per frame,
the MT9V011 will add additional blanking rows as needed. A second constraint is that
t
flicker, this means
must be a multiple of 1/100 of a second.
Reg0x0A Pixel Clock Speed
The pixel clock speed is set by Reg0x0A. The pixel clock period will be the number set
plus two master clock cycles. The default value is 0, which is equal to 2 master clock
cycles. With a master clock frequency of 27 MHz the PIXCLK frequency will be 13.5 MHz.
The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07
appropriately.
Reg0x0D Reset
This register is used to reset the sensor to its default, power-up state. To reset the
MT9V011, first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume
operation.
Reg0x1E Digital Zoom/True decimation
In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1
or 3 additional blank rows are added between each output row. This is designed to give
the controller logic time to repeat data to fill in a window that is either 2 or 4 times larger
with repeated data.
The pixel clock speed is not affected by this operation, and the output data for each pixel
is valid for either 2 or 4 pixel clocks. In zoom by 2 mode, every row is followed by a blank
row (with its own line valid, but all data bits = 0) of equal time. In zoom by 4 mode, every
row is followed by three blank rows. The combination of this register and an appropriate
change to the window sizing registers allows the user to zoom to a region of interest
without affecting the frame rate.
INT must be adjusted to avoid banding in the image from light flicker. Under 60 Hz
t
INT must be a multiple of 1/120 of a second. Under 50 Hz flicker,
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MT9V011 1/4-INCH VGA DIGITAL IMAGE SENSOR
Aptina reserves the right to change products or specifications without notice.
©2009 Aptina Imaging Corporation. All rights reserved.
Preliminary
t
INT