atr0620 ATMEL Corporation, atr0620 Datasheet - Page 11

• Manufacturer Part Number: atr0620
• Description: Gps Baseband Processor - Atmel Corporation
• Manufacturer: ATMEL Corporation

7. USART2: Universal Synchronous/ Asynchronous Receiver/Transmitter
8. SPI: Serial Peripheral Interface
9. WD: Watchdog Timer
10. PMC: Power Manager Controller
11. CLM: Clock Manager
4574CS–GPS–05/05
The ATR0620 provides three identical, full-duplex, universal synchronous/asynchronous
receiver/transmitters that interface to the APB and are connected to the peripheral data
controller.
The main features are:
The ATR0620 features an SPI, which provides communication with external devices in master or
slave mode. The SPI has four external chip selects that can be connected to up to 15 devices.
The data length is programmable from 8- to 16-bit. The PDC is used to move data directly
between memory and SPI without CPU intervention for maximum real-time processing
throughput.
The ATR0620 features an internal watchdog timer, which can be used to guard against system
lock-up if the software becomes trapped in a deadlock. The watchdog timer can be programmed
to generate an interrupt or an internal reset.
The power management controller allows optimization of power consumption. The PMC
enables/disables the clock inputs to most of the peripherals as well as to the ARM processor.
When the ARM clock is disabled, the current instruction is processed before the clock is
stopped. The clock can be re-enabled by any enabled interrupt or by a hardware reset. When a
peripheral clock is disabled, the clock is immediately stopped. When the clock is re-enabled the
peripheral resumes action where it left off.
Due to the static nature of the design, the contents of the on-chip RAM and registers for which
the clocks are disabled remain unchanged.
In addition to the Power Management Controller (PMC) the Clock Manager (CLM) is another
possibility to reduce power consumption. The clock manager provides fixed divided clocks for
the USARTs, SPI and watchdog timer and generates the master clock which can be divided.
The master clock is programmable for frequencies between 175 kHz and 23.1 MHz.
• Programmable baud rate generator
• Parity, framing and overrun error detection
• Line break generation and the detection
• Automatic echo, local loopback and remote loopback channel modes
• Multi-drop mode: address detection and generation
• Interrupt generation
• Two dedicated peripheral data controller channels
• 5-, 6-, 7-, 8-, and 9-bit character length
• Protocol ISO 7816 T = 0 and T = 1
ATR0620 [Preliminary]
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