hv110 Supertex, Inc., hv110 Datasheet - Page 5

• Manufacturer Part Number: hv110
• Description: Power-over-ethernet Interface Pd Controller Meets Ieee802.3af Tm Standard
• Manufacturer: Supertex, Inc.

PD Power Standards
According to the IEEE802.3af standards, the PD
must operate from 36V to account for a potential 8V
line drop across the impedance of the network
during inrush (400mA max current x 20Ω line-
impedance). The UVLO must allow a 44V max turn-
on and a 30V minimum turn off. A PD device may
draw a maximum power of 12.95W. The maximum
power that can be expected is limited by the 20Ω
line resistance carrying the 350mA current to the PD
at the minimum input voltage of 44V (power
delivered is 12.95W [{44 – (20*0.35)}*0.35].
PD Application
IEEE Electrical & Timing Requirements
Below are of the major features of HV110, some of
which are usually found only in PSE devices.
In addition to operating as a PD controller, HV110
can function as a redundant protective element to
assure
IEEE802.3af standard for the PD, even in cases
where the PD is powered from an auxiliary power
source, as shown in Figure 11.
Thermal Shutdown
HV110 is designed with a built in Thermal Shutdown
feature to assure higher levels of reliability. It will
shutdown if the temperature on the die reaches
140°C and will try to restart when the temperature
drops to 120°C.
Provides an internal current limit for inrush,
normal operation and overload conditions.
Limits the input current to less than 10µA that
will not interfere with Discovery from 2.6V to 10V
(with Zener as shown in Figure 1).
Meets the turn-on and turn-off thresholds for the
PD device & has a built-in 8V hysteresis (with
PNP transistor as shown in Figure 10).
Protects the device from thermal run away, with
thermal shut down and built in 9 sec restart
timer.
UVLO & POR provides hot-swapping/de-bounce
capabilities and inrush current limit.
PWRGD (active LOW) provides enable signal to
DC/DC converter.
Complies with the timing requirements for IEEE
802.3af standard.
Classification can be easily implemented, as
shown in Figure 9.
reliable
operation
and
compliance
to
5
Auto Restart
Any fault condition will cause the device to shut
down and enable a 9 second auto-restart timer. This
will occur indefinitely and is strong protection against
PSE error when the HV110 is used in PD
applications.
Note that a 9 second auto-restart will disconnect the
PD due to under current conditions, and will also
turn off the PSE, since the PSE will not see the
minimum current for greater than a period of 400ms
(350ms nominal).
PWRGD
The PWRGD (active low) pin is an open drain active
low MOSFET, (referred to V
when the gate voltage on the internal power
MOSFET reaches its full on voltage, provided that
the slew rate (V
being used.
Any fault condition will return PWRGD to a high
impedance state, turning off the HV110 and the
DC/DC converter. The PSE will also detect an
undercurrent condition for a period greater than
350ms (nominal), and will shut down by itself. It will
then wait for the next Discovery cycle.
Programmable UVLO and Hysteresis
ULVO is internally set through a 2.5Mohm and 116K
resistance divider in HV110. The default values of
UVLO are given in the Electrical Characteristics on
Page 2.
The UVLO circuit has a built in Hysteresis of 8V, to
enable stable operation during a UV condition. See
the section on Signature Detection for further details.
Internal MOSFET with Current Mirror
HV110 includes an internal 90V, 1ohm MOSFET.
The MOSFET current is mirrored to a current detect
circuit within the chip, utilizing a proprietary Supertex
algorithm and wastes almost no power. Elimination
of a sense resistor necessary with external power
switches means additional energy savings, providing
higher power output. Use of an on-board FET and
the thermal supervisor also leads to high reliability
compared to ICs that use external FETs whose
temperatures cannot be easily monitored.
PD Polarity
According to IEEE802.3af, PD shall be insensitive to
the polarity of the power supply and shall be able to
operate in Mode A and Mode B (cases when the
power is transferred through the signal leads and
slew
) timeout for large capacitor is not
NN
) which is enabled
HV110
A061104