hv110 Supertex, Inc., hv110 Datasheet - Page 6

• Manufacturer Part Number: hv110
• Description: Power-over-ethernet Interface Pd Controller Meets Ieee802.3af Tm Standard
• Manufacturer: Supertex, Inc.

spare leads). The connections to the 8-pin modulator
jack are different for Mode A and Mode B, polarity on
the pins can be different for Mode A.
Accommodating the different pin combinations and
polarity are beyond the scope of the PD Controller
IC, however these must be taken care of in the
system design. One of the ways of ensuring the
polarity protection is to use a small bridge rectifier in
between the 8-pin connector terminal and the PD
Controller.
Description of Operation
Signature Detection
During the Discovery process, the PSE applies a
voltage as described in the Discovery section on
Page 4 and determines if there is a PD connected at
the other end of the cable. The power loss across
the 25K signature resistor will be less than 120mW -
less than 1% of the power delivered to PD. It is
therefore not critical to disconnect the Signature
Resistor after the PD detection. However, this can
be easily accomplished by using a low cost bipolar
transistor and resistors. Note that the resistance of
the external circuit connected between the DRAIN
and VPP pin of the HV110 should be greater than
500kΩ (in the 2.8V – 10V Discovery voltage range)
for the signature detect to work properly (usually the
case with active loads like DC-DC converters).
Because of the zener diode connected to V
will be necessary to modify the internal UVLO
thresholds by using two external resistances as
shown in Figures 1, 9 and 11, to provide the UVLO
turn-off and turn-on voltages to meet the IEEE
802.3af standard. These two resistors perform dual
functions, UVLO voltage adjustments and also the
Signature Detection function (i.e. represent the 25k
impedance).
implementation using a PNP transistor which allows
the use of the HV110’s internal UV circuit.
Once the voltage exceeds 12V, the HV110 will turn
on and begin drawing a quiescent current of 1mA
typical.
Current Limit Functions
HV110 monitors the drain voltage and the current in
the load switch. During initial inrush if the drain does
not move more than 90% of input voltage within a
short-circuit timer period (t
device will conclude that a short circuit condition
exists, will turn off the internal FET and try to auto-
restart after a period of 9 seconds. If the initial inrush
period
IEEE802.3af standards then the internal FET is
ends
Figure
within
this
10
SC
period
shows
= 60ms), then the
as
a
per
different
PP
pin, it
the
6
turned fully on to minimize its on resistance and the
PWRGD pin will be pulled low, to the negative rail.
Figure 4 shows the turn on sequence of the HV110.
Once Discovery is complete, the PWRGD will be
high impedance. After the optional Classification is
complete and UVLO is satisfied, HV110 will provide
a controlled turn on of the internal switch (90V, 1Ω
Power
maximum value of 350mA (nominal).
During regular operation a fault condition can occur.
HV110 includes a current monitor that continuously
watches the FET current. If the current exceeds
350mA (nominal), fast-return to limit feature will be
activated and the over-current limit circuit will limit
the output current to 350mA (nominal), as shown in
Figure 5.
If the fault is not cleared within the nominal Over-
current timer limit of 60ms, HV110 will turn off the
Figure 5. PD Current jumps from 200mA to 400mA,
Figure 4. PD current jumps from 200mA to 400mA,
MOSFET),
Figure 4. Turn-on waveforms of the HV110
Controller shuts down in 60ms
Controller shuts down in 60ms
limiting
the
I
Input Current
DRAIN
nput Voltage
Input Current
I
PWRGD
nput Voltage
PWRGD
DRAIN
inrush
HV110
A061104
current