adv473 Analog Devices, Inc., adv473 Datasheet
adv473
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adv473 Summary of contents
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... MHz. It can also be used in other modes, including 15-bit true color and 8-bit pseudo or in- dexed color. The ADV473 is fully PS/2 and VGA register level compatible also capable of implementing IBM’s XGA standard. ...
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... ADV473–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage ...
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... OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO THE OUTPUT REMAINING WITHIN 1 LSB. 3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. Figure 2. Video Input/Output Timing –3– ADV473 = 10 pF 140 . L SET Units Conditions/Comments MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV473 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Voltage Reference Output. This output delivers a 1.2 V reference voltage from the device’s on-board voltage REFOUT reference generator normally connected directly to the V voltage reference, this pin may be left floating four ADV473s can be driven from V V Analog power. All V AA GND Analog Ground ...
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... CIRCUIT DESCRIPTION MPU Interface The ADV473 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. Three address decode lines, RS0–RS2, specify whether the MPU is accessing the address register, the color palette RAM, the overlay registers, or read mask register ...
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... When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical “0.” It should be noted that when the ADV473 is in 6-bit mode, full- scale output current will be reduced by approximately 1.5% relative to the 8-bit mode. This is the case since the 2 LSBs of each of the three DACs are always set to zero in 6-bit mode. – ...
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... ADV473 Command Register (CR) The ADV473 has an internal command register (CR). This reg- ister is 8 bits wide, CR0–CR7 and is directly mapped to the MPU data bus on the part, D0–D7. The command register can be written to or read from not initialized, therefore it must be set. Figure 4 shows what each bit of the CR register controls and shows the values it must be programmed to for various modes of operation ...
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... RAMs and pixel read mask register are bypassed. REV. A 15-Bit True-Color Bypass Mode Fifteen bits of pixel information may be input into the ADV473 every clock cycle. The 15 bits of pixel information (5 bits of red, 5 bits of green, and 5 bits of blue) are input via the R0–R7 and G0– ...
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... ADV473 MA V 26.67 1.000 92.5 IRE 9.05 0.340 7.5 IRE 7.62 0.286 40 IRE 0.00 0.000 NOTE: 75 DOUBLY TERMINATED LOAD, SETUP = 7.5 IRE, V RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 5. Composite Video Output Waveform (Setup = 7.5 IRE) Table VI. Video Output Truth Table (Setup = 7.5 IRE) Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC 1 ...
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... REV. A Digital Signal Interconnect The digital inputs to the ADV473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power AA plane ...
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... ADV473 Analog Signal Interconnect The ADV473 should be located as close as possible to the out- put connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection ...