gal6001 Lattice Semiconductor Corp., gal6001 Datasheet - Page 12

• Manufacturer Part Number: gal6001
• Description: High Performance E2 Cmos Fpla Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

The GAL6001 contains two E
is an AND array and the second is an OR array. These arrays are
described in detail below.
AND ARRAY
The AND array is organized as 78 inputs by 75 product term out-
puts. The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC
feedbacks, and ICLK comprise the 39 inputs to this array (each
available in true and complement forms). 64 product terms serve
as inputs to the OR array. The RESET product term generates the
RESET signal described in the Output and Buried Logic Macrocells
section. There are 10 output enable product terms which allow
device pins 14-23 to be bi-directional or tri-state.
OR ARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data (“D”) terms and 18
are enable/clock (“E”) terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one “D” term and one “E” term to each.
The programmable OR array offers unparalleled versatility in prod-
uct term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.
An electronic signature (ES) is provided in every GAL6001 device.
It contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The ES is included in checksum calculations. Changing the
ES will alter the checksum.
A security cell is provided in every GAL6001 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND and OR arrays.
This cell can be erased only during a bulk erase cycle, so the origi-
nal configuration can never be examined once this cell is pro-
grammed. The Electronic Signature is always available to the user,
regardless of the state of this control cell.
Array Description
Electronic Signature
Security Cell
2
reprogrammable arrays. The first
12
Before writing a new pattern into a previously programmed part,
the old pattern must first be erased. This erasure is done automati-
cally by the programming hardware as part of the programming
cycle and takes only 50 milliseconds.
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because in system operation, certain events
may occur that cause the logic to assume an illegal state: power-
up, brown out, line voltage glitches, etc. To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.
All of the registers in the GAL6001 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con-
tents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.
GAL6001 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos-
sibility of SCR induced latching.
GAL devices are designed with TTL level compatible input buffers.
These buffers, with their characteristically high impedance, load
driving logic much less than traditional bipolar devices. This al-
lows for a greater fan out from the driving logic.
GAL6001 devices do not possess active pull-ups within their input
structures. As a result, Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
Bulk Erase
Register Preload
Latch-Up Protection
Input Buffers
Specifications GAL6001